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b=pifQ5+ONvbZjCiev QRRqtVltMrlsLArcgvYFc42JNgH3Vw+UvBG3zXQyQ9nBDtU6PIO2za4+nR4VHr7O IL/bRx72UQCcmmGpoQrflSpP13clUd8i6yFYx4pKLXoPqhbKh6Kure6xzyfCddoy GBzHtNFDtztVqahvH18e5EzhgtjSU+urouq044f2TQt6ER7EPJPqf3kjYIhzaInf gi+NvTyVRl2NYMT6D61v9BryeuFl0Aw4x0KcIuMIQHtjOnPrl4zYEC/xuPJG2oYU ypLQEy0Es7iMnIWXUoFRBsAMTpmakAqVnvkUozqc8ruLw9kqWRo+Kv54ufKHDZM4 SebNrg== From: Michael Kowal To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, clg@kaod.org, fbarrat@linux.ibm.com, npiggin@gmail.com, milesg@linux.ibm.com Subject: [PATCH v4 12/14] pnv/xive: Update PIPR when updating CPPR Date: Fri, 13 Sep 2024 11:16:57 -0500 Message-Id: <20240913161659.1981-13-kowal@linux.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240913161659.1981-1-kowal@linux.ibm.com> References: <20240913161659.1981-1-kowal@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ZocYHg1OerphJRiWloSY7lFA6CyK1-F0 X-Proofpoint-ORIG-GUID: voR8d9YlGm399D8rzWAWzUnztrd27aW_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-13_11,2024-09-13_02,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=854 lowpriorityscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409130113 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1726244413505116600 From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority = is more privileged") Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5c5c3a2dd6..738eaf624d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -89,7 +89,6 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t = ring) =20 /* Reset the pending buffer bit */ alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr); - regs[TM_PIPR] =3D ipb_to_pipr(alt_regs[TM_IPB]); =20 /* Drop Exception bit */ regs[TM_NSR] &=3D ~mask; @@ -143,6 +142,8 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t rin= g) static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { uint8_t *regs =3D &tctx->regs[ring]; + uint8_t pipr_min; + uint8_t ring_min; =20 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, regs[TM_IPB], regs[TM_PIPR], @@ -154,8 +155,37 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) =20 tctx->regs[ring + TM_CPPR] =3D cppr; =20 + /* + * Recompute the PIPR based on local pending interrupts. The PHYS + * ring must take the minimum of both the PHYS and POOL PIPR values. + */ + pipr_min =3D ipb_to_pipr(regs[TM_IPB]); + ring_min =3D ring; + + /* PHYS updates also depend on POOL values */ + if (ring =3D=3D TM_QW3_HV_PHYS) { + uint8_t *pool_regs =3D &tctx->regs[TM_QW2_HV_POOL]; + + /* POOL values only matter if POOL ctx is valid */ + if (pool_regs[TM_WORD2] & 0x80) { + + uint8_t pool_pipr =3D ipb_to_pipr(pool_regs[TM_IPB]); + + /* + * Determine highest priority interrupt and + * remember which ring has it. + */ + if (pool_pipr < pipr_min) { + pipr_min =3D pool_pipr; + ring_min =3D TM_QW2_HV_POOL; + } + } + } + + regs[TM_PIPR] =3D pipr_min; + /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring); + xive_tctx_notify(tctx, ring_min); } =20 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) --=20 2.43.0