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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42d9b16bfbfsm29152325e9.22.2024.09.13.08.14.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:14:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726240461; x=1726845261; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sMpuvKSijMzza9jyYi3YKFy2MNvxfWsjj0r4/UrtdJo=; b=by1y0Ywcz/1Eb+IL7mSeHkuMLcmSASAIdSLkwszu5qP3kKMRG8J5oI3OQaRkSjhjqG PSQjuAU+xotrfRvVIDv+m5v4QP1CaWoCIp9o+2VgfD0QAEUEqb1a8ovv4lvGd3K6x9EH Q81thgsvtLS1E8cIz6EI8H4L1RvhriVYwydikHh8TucJVoBpcIR/P0If1TGz8DpN5Cfm zmOAsv0mg001EJP0gJrsHibUQmRukoch3ujfU7ug1UXxDxwAslwbANmtSnh+Q1IkCX7h N5sv8iMJdd/lC1J5O1QsEeBLHrYC2aQJZOgad4B9AMm1ObT8+7TiKg0byPK9C6xkSayj UpSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726240461; x=1726845261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMpuvKSijMzza9jyYi3YKFy2MNvxfWsjj0r4/UrtdJo=; b=ciU4XIx1GBQ1PGs1zjMCrZg/Fr2DbNwT6aZFxZfLPRN+hHPqjC0TOH+aKmTd2hdKI+ M52ji0Et15vC+Tp1SO+fj2hsQk3OzlXy3FT0rUON63nWy5mRoarDQnRk+Qw+uwXn6xxb fjIiZ0YHs7xnUlviYB8u8BnsLE10Z+yEgEFX3ZnbTauZ6drX7ehI3sz611B4Xo/cYAVz voNQGxHqqpd3MAvzRzJeey5ocb9ycSZNT9d09AC5Bbvls3eCDsaSD4WAElEbtaPjhnfV 33n8HNMBn/YEVtyi0BmB0K+VR0fGld1Un1muvCZfb8xRcfaBYRSe9G/dj6uiXxxMb/a+ gZ8A== X-Gm-Message-State: AOJu0YzKXqpsHKfdPZOP+eaZQVLRETMGyw5ThxPM5DOkYLQcT3vNamhy sgP1SGtcYRG3Iwz0ENHLl2CY9ikijZ1T2336p6eYwVo/0sz7i+DnmibUecKgNg7auo8otlxUxfZ 6 X-Google-Smtp-Source: AGHT+IG0hfeezERxpVZcQi+LotZP+VnGZ7siNaa7pVzNaHWp2kmsHJksmim+ZVTIekqPfARImtAhiw== X-Received: by 2002:a05:600c:3b8e:b0:42c:b377:3f76 with SMTP id 5b1f17b1804b1-42cdb54e68fmr57889745e9.17.1726240461329; Fri, 13 Sep 2024 08:14:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/27] target/arm/tcg: refine cache descriptions with a wrapper Date: Fri, 13 Sep 2024 16:14:00 +0100 Message-Id: <20240913151411.2167922-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240913151411.2167922-1-peter.maydell@linaro.org> References: <20240913151411.2167922-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726240538101116600 From: Alireza Sanaee This patch allows for easier manipulation of the cache description register, CCSIDR. Which is helpful for testing as well. Currently, numbers get hard-coded and might be prone to errors. Therefore, this patch adds a wrapper for different types of CPUs available in tcg to decribe caches. One function `make_ccsidr` supports two cases by carrying a parameter as FORMAT that can be LEGACY and CCIDX which determines the specification of the register. For CCSIDR register, 32 bit version follows specification [1]. Conversely, 64 bit version follows specification [2]. [1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition, https://developer.arm.com/documentation/ddi0406 [2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture, https://developer.arm.com/documentation/ddi0487/latest/ Signed-off-by: Alireza Sanaee Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20240903144550.280-1-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 50 ++++++++++++++++++ target/arm/cpu64.c | 19 ++++--- target/arm/tcg/cpu64.c | 108 +++++++++++++++++++------------------- 3 files changed, 117 insertions(+), 60 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index cfb82c23cad..04ce2818263 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -21,6 +21,7 @@ #define TARGET_ARM_FEATURES_H =20 #include "hw/registerfields.h" +#include "qemu/host-utils.h" =20 /* * Naming convention for isar_feature functions: @@ -1027,6 +1028,55 @@ static inline bool isar_feature_any_evt(const ARMISA= Registers *id) return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); } =20 +typedef enum { + CCSIDR_FORMAT_LEGACY, + CCSIDR_FORMAT_CCIDX, +} CCSIDRFormat; + +static inline uint64_t make_ccsidr(CCSIDRFormat format, unsigned assoc, + unsigned linesize, unsigned cachesize, + uint8_t flags) +{ + unsigned lg_linesize =3D ctz32(linesize); + unsigned sets; + uint64_t ccsidr =3D 0; + + assert(assoc !=3D 0); + assert(is_power_of_2(linesize)); + assert(lg_linesize >=3D 4 && lg_linesize <=3D 7 + 4); + + /* sets * associativity * linesize =3D=3D cachesize. */ + sets =3D cachesize / (assoc * linesize); + assert(cachesize % (assoc * linesize) =3D=3D 0); + + if (format =3D=3D CCSIDR_FORMAT_LEGACY) { + /* + * The 32-bit CCSIDR format is: + * [27:13] number of sets - 1 + * [12:3] associativity - 1 + * [2:0] log2(linesize) - 4 + * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 = bytes, etc + */ + ccsidr =3D deposit32(ccsidr, 28, 4, flags); + ccsidr =3D deposit32(ccsidr, 13, 15, sets - 1); + ccsidr =3D deposit32(ccsidr, 3, 10, assoc - 1); + ccsidr =3D deposit32(ccsidr, 0, 3, lg_linesize - 4); + } else { + /* + * The 64-bit CCSIDR_EL1 format is: + * [55:32] number of sets - 1 + * [23:3] associativity - 1 + * [2:0] log2(linesize) - 4 + * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 = bytes, etc + */ + ccsidr =3D deposit64(ccsidr, 32, 24, sets - 1); + ccsidr =3D deposit64(ccsidr, 3, 21, assoc - 1); + ccsidr =3D deposit64(ccsidr, 0, 3, lg_linesize - 4); + } + + return ccsidr; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 262a1d6c0bb..458d1cee012 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "cpregs.h" #include "qemu/module.h" +#include "qemu/units.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "sysemu/qtest.h" @@ -642,9 +643,12 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.dbgdevid1 =3D 0x2; cpu->isar.reset_pmcr_el0 =3D 0x41013000; cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + /* 32KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + /* 48KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, = 2); + /* 2048KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, = 7); cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; @@ -700,9 +704,12 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.dbgdevid1 =3D 0x1; cpu->isar.reset_pmcr_el0 =3D 0x41033000; cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1024KB L2 cache */ + /* 32KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + /* 32KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, = 2); + /* 1024KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, = 7); cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 79258a7c928..b9f34f044d0 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -29,32 +29,6 @@ #include "cpu-features.h" #include "cpregs.h" =20 -static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, - unsigned cachesize) -{ - unsigned lg_linesize =3D ctz32(linesize); - unsigned sets; - - /* - * The 64-bit CCSIDR_EL1 format is: - * [55:32] number of sets - 1 - * [23:3] associativity - 1 - * [2:0] log2(linesize) - 4 - * so 0 =3D=3D 16 bytes, 1 =3D=3D 32 bytes, 2 =3D=3D 64 byte= s, etc - */ - assert(assoc !=3D 0); - assert(is_power_of_2(linesize)); - assert(lg_linesize >=3D 4 && lg_linesize <=3D 7 + 4); - - /* sets * associativity * linesize =3D=3D cachesize. */ - sets =3D cachesize / (assoc * linesize); - assert(cachesize % (assoc * linesize) =3D=3D 0); - - return ((uint64_t)(sets - 1) << 32) - | ((assoc - 1) << 3) - | (lg_linesize - 4); -} - static void aarch64_a35_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -106,9 +80,12 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.reset_pmcr_el0 =3D 0x410a3000; =20 /* From B2.29 Cache ID registers */ - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x703fe03a; /* 512KB L2 cache */ + /* 32KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + /* 32KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB= , 7); =20 /* From B3.5 VGIC Type register */ cpu->gic_num_lrs =3D 4; @@ -272,9 +249,12 @@ static void aarch64_a55_initfn(Object *obj) cpu->revidr =3D 0; =20 /* From B2.23 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x200fe01a; /* 32KB L1 icache */ - cpu->ccsidr[2] =3D 0x703fe07a; /* 512KB L2 cache */ + /* 32KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + /* 32KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB= , 7); =20 /* From B2.96 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -338,9 +318,12 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.dbgdevid1 =3D 0x2; cpu->isar.reset_pmcr_el0 =3D 0x41023000; cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + /* 32KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + /* 48KB L1 dcache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, = 2); + /* 1MB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, = 7); cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; @@ -397,9 +380,12 @@ static void aarch64_a76_initfn(Object *obj) cpu->revidr =3D 0; =20 /* From B2.18 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); =20 /* From B2.93 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -449,9 +435,12 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64isar1 =3D 0x0000000000010001; cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; cpu->clidr =3D 0x0000000080000023; - cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 2); + /* 8MB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB,= 7); cpu->dcz_blocksize =3D 6; /* 256 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; @@ -637,9 +626,12 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->revidr =3D 0; =20 /* From B2.23 CCSIDR_EL1 */ - cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + /* 1MB L2 dcache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7= ); =20 /* From B2.98 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -721,9 +713,12 @@ static void aarch64_neoverse_v1_initfn(Object *obj) * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. * L3: No L3 (this matches the CLIDR_EL1 value). */ - cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ - cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */ - cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0= ); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D cpu->ccsidr[0]; + /* 1MB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); =20 /* From 3.2.115 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -959,9 +954,12 @@ static void aarch64_a710_initfn(Object *obj) * L1: 4-way set associative 64-byte line size, total either 32K or 64= K. * L2: 8-way set associative 64 byte line size, total either 256K or 5= 12K. */ - cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ - cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */ - cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ + /* L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0= ); + /* L1 icache */ + cpu->ccsidr[1] =3D cpu->ccsidr[0]; + /* L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, = 0); =20 /* FIXME: Not documented -- copied from neoverse-v1 */ cpu->reset_sctlr =3D 0x30c50838; @@ -1057,10 +1055,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj) * L1: 4-way set associative 64-byte line size, total 64K. * L2: 8-way set associative 64 byte line size, total either 512K or 1= 024K. */ - cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ - cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */ - cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ - + /* L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0= ); + /* L1 icache */ + cpu->ccsidr[1] =3D cpu->ccsidr[0]; + /* L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, = 0); /* FIXME: Not documented -- copied from neoverse-v1 */ cpu->reset_sctlr =3D 0x30c50838; =20 --=20 2.34.1