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Thu, 12 Sep 2024 16:53:49 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Alistair Francis Subject: [PATCH v14 18/20] disas/riscv: enable disassembly for zicfiss instructions Date: Thu, 12 Sep 2024 16:53:18 -0700 Message-ID: <20240912235320.3768582-19-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240912235320.3768582-1-debug@rivosinc.com> References: <20240912235320.3768582-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=debug@rivosinc.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1726185457378116600 Content-Type: text/plain; charset="utf-8" Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 40 +++++++++++++++++++++++++++++++++++++++- disas/riscv.h | 1 + 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 2942a5800f..0f9ecd8a14 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -977,6 +977,11 @@ typedef enum { rv_op_wrs_sto =3D 946, rv_op_wrs_nto =3D 947, rv_op_lpad =3D 948, + rv_op_sspush =3D 949, + rv_op_sspopchk =3D 950, + rv_op_ssrdp =3D 951, + rv_op_ssamoswap_w =3D 952, + rv_op_ssamoswap_d =3D 953, } rv_op; =20 /* register names */ @@ -2238,6 +2243,11 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, { "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 }, + { "sspush", rv_codec_r, rv_fmt_rs2, NULL, 0, 0, 0 }, + { "sspopchk", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, + { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 }, + { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, + { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -2255,6 +2265,7 @@ static const char *csr_name(int csrno) case 0x0009: return "vxsat"; case 0x000a: return "vxrm"; case 0x000f: return "vcsr"; + case 0x0011: return "ssp"; case 0x0015: return "seed"; case 0x0017: return "jvt"; case 0x0040: return "uscratch"; @@ -3081,6 +3092,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 66: op =3D rv_op_amoor_w; break; case 67: op =3D rv_op_amoor_d; break; case 68: op =3D rv_op_amoor_q; break; + case 74: op =3D rv_op_ssamoswap_w; break; + case 75: op =3D rv_op_ssamoswap_d; break; case 96: op =3D rv_op_amoand_b; break; case 97: op =3D rv_op_amoand_h; break; case 98: op =3D rv_op_amoand_w; break; @@ -4034,7 +4047,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 3: op =3D rv_op_csrrc; break; case 4: if (dec->cfg->ext_zimop) { - int imm_mop5, imm_mop3; + int imm_mop5, imm_mop3, reg_num; if ((extract32(inst, 22, 10) & 0b1011001111) =3D=3D 0b1000000111) { imm_mop5 =3D deposit32(deposit32(extract32(inst, 2= 0, 2), @@ -4042,11 +4055,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) extract32(inst, 26,= 2)), 4, 1, extract32(inst, 30, 1)); op =3D rv_mop_r_0 + imm_mop5; + /* if zicfiss enabled and mop5 is shadow stack */ + if (dec->cfg->ext_zicfiss && + ((imm_mop5 & 0b11100) =3D=3D 0b11100)) { + /* rs1=3D0 means ssrdp */ + if ((inst & (0b011111 << 15)) =3D=3D 0) { + op =3D rv_op_ssrdp; + } + /* rd=3D0 means sspopchk */ + reg_num =3D (inst >> 15) & 0b011111; + if (((inst & (0b011111 << 7)) =3D=3D 0) && + ((reg_num =3D=3D 1) || (reg_num =3D=3D= 5))) { + op =3D rv_op_sspopchk; + } + } } else if ((extract32(inst, 25, 7) & 0b1011001) =3D=3D 0b1000001) { imm_mop3 =3D deposit32(extract32(inst, 26, 2), 2, 1, extract32(inst, 30, 1)); op =3D rv_mop_rr_0 + imm_mop3; + /* if zicfiss enabled and mop3 is shadow stack */ + if (dec->cfg->ext_zicfiss && + ((imm_mop3 & 0b111) =3D=3D 0b111)) { + /* rs1=3D0 and rd=3D0 means sspush */ + reg_num =3D (inst >> 20) & 0b011111; + if (((inst & (0b011111 << 15)) =3D=3D 0) && + ((inst & (0b011111 << 7)) =3D=3D 0) && + ((reg_num =3D=3D 1) || (reg_num =3D=3D= 5))) { + op =3D rv_op_sspush; + } + } } } break; diff --git a/disas/riscv.h b/disas/riscv.h index 1182457aff..4895c5a301 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -224,6 +224,7 @@ enum { =20 #define rv_fmt_none "O\t" #define rv_fmt_rs1 "O\t1" +#define rv_fmt_rs2 "O\t2" #define rv_fmt_offset "O\to" #define rv_fmt_pred_succ "O\tp,s" #define rv_fmt_rs1_rs2 "O\t1,2" --=20 2.45.0