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b=lVn7DXlNShbqGYV2 PsQtKhFoEKy/fAtV4b3puzZ+jBwyWOEhFXRkmGMIvrjhTpBabVOfc9C0VMopQY9T YeqLCXAShYaXqlL5tj/hRWkzGjJqHMcH748ptOuk0bZZOvDNNDwrSBPXtWu8YBJb HwF98wTEuFvO8Yq99sPsuvHNYS+oGOY8q1mtmiGGlKpUz1pbGuOiVzN1vpMClBmR mo0iFMi6vNLI++YfjAGqZS5EKpv7XAPn96JC0XNxuDLm5neQ7OaSbK3bdpVsUUOI 8pFB3gSwr/RVgNsBz+LtalaIVJapfbZa0+2hzFoSxe5IEH39giPEMzwXyvNvRwRQ 61fQaw== From: Michael Kowal To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, clg@kaod.org, fbarrat@linux.ibm.com, npiggin@gmail.com, milesg@linux.ibm.com Subject: [PATCH v3 08/14] ppc/xive2: Support "Pull Thread Context to Register" operation Date: Thu, 12 Sep 2024 15:50:22 -0500 Message-Id: <20240912205028.15854-9-kowal@linux.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240912205028.15854-1-kowal@linux.ibm.com> References: <20240912205028.15854-1-kowal@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: LzZYuOHqmpJ4K6NVe1oHxha7i3zMRZ3q X-Proofpoint-GUID: h4VYMHmoO02AG-T8ERQ3D43R4_GAx-xM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-12_07,2024-09-12_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120149 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1726174332993116600 From: Glenn Miles Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Return the number of bytes requested in step 1 to a register. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/xive_regs.h | 2 ++ hw/intc/xive.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index f8f05deafd..558a5ae742 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -101,6 +101,7 @@ #define TM_QW3W2_LP PPC_BIT32(6) #define TM_QW3W2_LE PPC_BIT32(7) #define TM_QW3W2_T PPC_BIT32(31) +#define TM_QW3B8_VT PPC_BIT8(0) =20 /* * In addition to normal loads to "peek" and writes (only when invalid) @@ -128,6 +129,7 @@ #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate P= ool */ /* context to reg = */ #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg = */ +#define TM_SPC_PULL_PHYS_CTX 0x838 /* Pull phys ctx to reg = */ #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to od= d */ /* line = */ #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line = */ diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 6229a6f870..5b66a3aec5 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -179,6 +179,17 @@ static uint64_t xive_tm_pull_pool_ctx(XivePresenter *x= ptr, XiveTCTX *tctx, return qw2w2; } =20 +static uint64_t xive_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) +{ + uint8_t qw3b8_prev =3D tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; + uint8_t qw3b8; + + qw3b8 =3D qw3b8_prev & ~TM_QW3B8_VT; + tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] =3D qw3b8; + return qw3b8; +} + static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr of= fset, uint64_t value, unsigned size) { @@ -527,6 +538,8 @@ static const XiveTmOp xive_tm_operations[] =3D { xive_tm_pull_pool_ctx= }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_ctx= }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, + xive_tm_pull_phys_ctx= }, }; =20 static const XiveTmOp xive2_tm_operations[] =3D { @@ -566,6 +579,8 @@ static const XiveTmOp xive2_tm_operations[] =3D { xive_tm_pull_pool_ctx= }, { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_= ol, NULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL, + xive_tm_pull_phys_ctx= }, }; =20 static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, --=20 2.43.0