From nobody Sun Nov 24 05:39:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146658879686.933512303054; Thu, 12 Sep 2024 06:10:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZh-00030s-Vm; Thu, 12 Sep 2024 09:09:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZd-0002zw-3p for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZb-0004pS-CJ for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:24 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxOOkA6OJm5OQFAA--.12495S3; Thu, 12 Sep 2024 21:09:20 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S3; Thu, 12 Sep 2024 21:09:20 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 1/7] target/loongarch: Add compatible support about VM reboot Date: Thu, 12 Sep 2024 20:51:26 +0800 Message-Id: <20240912125132.268802-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146893492116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only if its value is equal to zero for boot cpu, it causes reboot issue. Since CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it. Add workaround to clear CSR registers relative with TLB in function loongarch_cpu_reset_hold(), so that VM can reboot with edk2-stable202408 UEFI bios. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-Id: <20240827035807.3326293-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 5e85b9dbef..115922113a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -549,6 +549,20 @@ static void loongarch_cpu_reset_hold(Object *obj, Rese= tType type) env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); env->CSR_MERRCTL =3D FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); env->CSR_TID =3D cs->cpu_index; + /* + * Workaround for edk2-stable202408, CSR PGD register is set only if + * its value is equal to zero for boot cpu, it causes reboot issue. + * + * Here clear CSR registers relative with TLB. + */ + env->CSR_PGDH =3D 0; + env->CSR_PGDL =3D 0; + env->CSR_PWCL =3D 0; + env->CSR_PWCH =3D 0; + env->CSR_STLBPS =3D 0; + env->CSR_EENTRY =3D 0; + env->CSR_TLBRENTRY =3D 0; + env->CSR_MERRENTRY =3D 0; =20 for (n =3D 0; n < 4; n++) { env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); --=20 2.34.1