From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146658879686.933512303054; Thu, 12 Sep 2024 06:10:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZh-00030s-Vm; Thu, 12 Sep 2024 09:09:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZd-0002zw-3p for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZb-0004pS-CJ for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:24 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxOOkA6OJm5OQFAA--.12495S3; Thu, 12 Sep 2024 21:09:20 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S3; Thu, 12 Sep 2024 21:09:20 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 1/7] target/loongarch: Add compatible support about VM reboot Date: Thu, 12 Sep 2024 20:51:26 +0800 Message-Id: <20240912125132.268802-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146893492116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only if its value is equal to zero for boot cpu, it causes reboot issue. Since CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it. Add workaround to clear CSR registers relative with TLB in function loongarch_cpu_reset_hold(), so that VM can reboot with edk2-stable202408 UEFI bios. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-Id: <20240827035807.3326293-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 5e85b9dbef..115922113a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -549,6 +549,20 @@ static void loongarch_cpu_reset_hold(Object *obj, Rese= tType type) env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); env->CSR_MERRCTL =3D FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); env->CSR_TID =3D cs->cpu_index; + /* + * Workaround for edk2-stable202408, CSR PGD register is set only if + * its value is equal to zero for boot cpu, it causes reboot issue. + * + * Here clear CSR registers relative with TLB. + */ + env->CSR_PGDH =3D 0; + env->CSR_PGDL =3D 0; + env->CSR_PWCL =3D 0; + env->CSR_PWCH =3D 0; + env->CSR_STLBPS =3D 0; + env->CSR_EENTRY =3D 0; + env->CSR_TLBRENTRY =3D 0; + env->CSR_MERRENTRY =3D 0; =20 for (n =3D 0; n < 4; n++) { env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); --=20 2.34.1 From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146658752185.79148641956067; Thu, 12 Sep 2024 06:10:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZo-0003Rb-BS; Thu, 12 Sep 2024 09:09:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZg-00030j-Qf for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:28 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZb-0004pV-0m for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:25 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dx1ugA6OJm5uQFAA--.12514S3; Thu, 12 Sep 2024 21:09:20 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S4; Thu, 12 Sep 2024 21:09:20 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 2/7] hw/loongarch: Remove default enable with VIRTIO_VGA device Date: Thu, 12 Sep 2024 20:51:27 +0800 Message-Id: <20240912125132.268802-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146854323116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao For virtio VGA deivce libvirt will select VIRTIO_VGA firstly rather than VIRTIO_GPU, VIRTIO_VGA device supports frame buffer however it requires legacy VGA compatible support. Frame buffer area 0xa0000 -- 0xc0000 conflicts with low memory area 0 -- 0x10000000. Here remove default support for VIRTIO_VGA device, VIRTIO_GPU is prefered on LoongArch system. For frame buffer video card support, standard VGA can be used. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-Id: <20240823073050.2619484-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- hw/loongarch/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 0de713a439..9c69170968 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -5,7 +5,6 @@ config LOONGARCH_VIRT select DEVICE_TREE select PCI select PCI_EXPRESS_GENERIC_BRIDGE - imply VIRTIO_VGA imply PCI_DEVICES imply NVDIMM imply TPM_TIS_SYSBUS --=20 2.34.1 From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17261466730606.570917893077649; Thu, 12 Sep 2024 06:11:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZm-0003G1-1e; Thu, 12 Sep 2024 09:09:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZg-00030l-RI for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:28 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZd-0004pZ-0S for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:26 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxTOoB6OJm6eQFAA--.13699S3; Thu, 12 Sep 2024 21:09:21 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S5; Thu, 12 Sep 2024 21:09:20 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 3/7] target/loongarch/kvm: Add vCPU reset function Date: Thu, 12 Sep 2024 20:51:28 +0800 Message-Id: <20240912125132.268802-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146907248116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao KVM provides interface KVM_REG_LOONGARCH_VCPU_RESET to reset vCPU, it can be used to clear internal state about kvm kernel. vCPU reset function is added here for kvm mode. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-Id: <20240822022827.2273534-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.c | 2 +- target/loongarch/kvm/kvm.c | 5 ++++- target/loongarch/kvm/kvm_loongarch.h | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 115922113a..6a569285b8 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -577,7 +577,7 @@ static void loongarch_cpu_reset_hold(Object *obj, Reset= Type type) memset(env->tlb, 0, sizeof(env->tlb)); #endif if (kvm_enabled()) { - kvm_arch_reset_vcpu(env); + kvm_arch_reset_vcpu(cs); } #endif =20 diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index e1be6a6959..4786cd5efa 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -476,9 +476,12 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs) return ret; } =20 -void kvm_arch_reset_vcpu(CPULoongArchState *env) +void kvm_arch_reset_vcpu(CPUState *cs) { + CPULoongArchState *env =3D cpu_env(cs); + env->mp_state =3D KVM_MP_STATE_RUNNABLE; + kvm_set_one_reg(cs, KVM_REG_LOONGARCH_VCPU_RESET, 0); } =20 static int kvm_loongarch_get_mpstate(CPUState *cs) diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kv= m_loongarch.h index d945b6bb82..1051a341ec 100644 --- a/target/loongarch/kvm/kvm_loongarch.h +++ b/target/loongarch/kvm/kvm_loongarch.h @@ -11,6 +11,6 @@ #define QEMU_KVM_LOONGARCH_H =20 int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level); -void kvm_arch_reset_vcpu(CPULoongArchState *env); +void kvm_arch_reset_vcpu(CPUState *cs); =20 #endif --=20 2.34.1 From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146658780363.72036052729163; Thu, 12 Sep 2024 06:10:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZj-00038V-E3; Thu, 12 Sep 2024 09:09:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZg-00030m-RQ for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:28 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZd-0004pi-10 for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:27 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dx1ugC6OJm6+QFAA--.12516S3; Thu, 12 Sep 2024 21:09:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S6; Thu, 12 Sep 2024 21:09:21 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 4/7] target/loongarch: Support QMP dump-guest-memory Date: Thu, 12 Sep 2024 20:51:29 +0800 Message-Id: <20240912125132.268802-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146886205116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao Add the support needed for creating prstatus elf notes. This allows us to use QMP dump-guest-memory. Now ELF notes of LoongArch only supports general elf notes, LSX and LASX is not supported, since it is mainly used to dump guest memory. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Tested-by: Song Gao Message-Id: <20240822065245.2286214-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/arch_dump.c | 167 +++++++++++++++++++++++++++++++++++ target/loongarch/cpu.c | 1 + target/loongarch/internals.h | 2 + target/loongarch/meson.build | 1 + 4 files changed, 171 insertions(+) create mode 100644 target/loongarch/arch_dump.c diff --git a/target/loongarch/arch_dump.c b/target/loongarch/arch_dump.c new file mode 100644 index 0000000000..4986db970e --- /dev/null +++ b/target/loongarch/arch_dump.c @@ -0,0 +1,167 @@ +/* + * Support for writing ELF notes for LoongArch architectures + * + * Copyright (c) 2023 Loongarch Technology + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "elf.h" +#include "sysemu/dump.h" +#include "internals.h" + +/* struct user_pt_regs from arch/loongarch/include/uapi/asm/ptrace.h */ +struct loongarch_user_regs { + uint64_t gpr[32]; + uint64_t pad1[1]; + /* Special CSR registers. */ + uint64_t csr_era; + uint64_t csr_badv; + uint64_t pad2[10]; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct loongarch_user_regs) !=3D 360); + +/* struct elf_prstatus from include/uapi/linux/elfcore.h */ +struct loongarch_elf_prstatus { + char pad1[32]; /* 32 =3D=3D offsetof(struct elf_prstatus, pr_pid) */ + uint32_t pr_pid; + /* + * 76 =3D=3D offsetof(struct elf_prstatus, pr_reg) - + * offsetof(struct elf_prstatus, pr_ppid) + */ + char pad2[76]; + struct loongarch_user_regs pr_reg; + uint32_t pr_fpvalid; + char pad3[4]; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct loongarch_elf_prstatus) !=3D 480); + +/* struct user_fp_state from arch/loongarch/include/uapi/asm/ptrace.h */ +struct loongarch_fpu_struct { + uint64_t fpr[32]; + uint64_t fcc; + unsigned int fcsr; +} QEMU_PACKED; + +QEMU_BUILD_BUG_ON(sizeof(struct loongarch_fpu_struct) !=3D 268); + +struct loongarch_note { + Elf64_Nhdr hdr; + char name[8]; /* align_up(sizeof("CORE"), 4) */ + union { + struct loongarch_elf_prstatus prstatus; + struct loongarch_fpu_struct fpu; + }; +} QEMU_PACKED; + +#define LOONGARCH_NOTE_HEADER_SIZE offsetof(struct loongarch_note, prstatu= s) +#define LOONGARCH_PRSTATUS_NOTE_SIZE = \ + (LOONGARCH_NOTE_HEADER_SIZE + sizeof(struct loongarch_elf_prstatus)) +#define LOONGARCH_PRFPREG_NOTE_SIZE = \ + (LOONGARCH_NOTE_HEADER_SIZE + sizeof(struct loongarch_fpu_struct)) + +static void loongarch_note_init(struct loongarch_note *note, DumpState *s, + const char *name, Elf64_Word namesz, + Elf64_Word type, Elf64_Word descsz) +{ + memset(note, 0, sizeof(*note)); + + note->hdr.n_namesz =3D cpu_to_dump32(s, namesz); + note->hdr.n_descsz =3D cpu_to_dump32(s, descsz); + note->hdr.n_type =3D cpu_to_dump32(s, type); + + memcpy(note->name, name, namesz); +} + +static int loongarch_write_elf64_fprpreg(WriteCoreDumpFunction f, + CPULoongArchState *env, int cpuid, + DumpState *s) +{ + struct loongarch_note note; + int ret, i; + + loongarch_note_init(¬e, s, "CORE", 5, NT_PRFPREG, sizeof(note.fpu)); + note.fpu.fcsr =3D cpu_to_dump64(s, env->fcsr0); + + for (i =3D 0; i < 8; i++) { + note.fpu.fcc |=3D env->cf[i] << (8 * i); + } + note.fpu.fcc =3D cpu_to_dump64(s, note.fpu.fcc); + + for (i =3D 0; i < 32; ++i) { + note.fpu.fpr[i] =3D cpu_to_dump64(s, env->fpr[i].vreg.UD[0]); + } + + ret =3D f(¬e, LOONGARCH_PRFPREG_NOTE_SIZE, s); + if (ret < 0) { + return -1; + } + + return 0; +} + +int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, DumpState *s) +{ + struct loongarch_note note; + CPULoongArchState *env =3D &LOONGARCH_CPU(cs)->env; + int ret, i; + + loongarch_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, + sizeof(note.prstatus)); + note.prstatus.pr_pid =3D cpu_to_dump32(s, cpuid); + note.prstatus.pr_fpvalid =3D cpu_to_dump32(s, 1); + + for (i =3D 0; i < 32; ++i) { + note.prstatus.pr_reg.gpr[i] =3D cpu_to_dump64(s, env->gpr[i]); + } + note.prstatus.pr_reg.csr_era =3D cpu_to_dump64(s, env->CSR_ERA); + note.prstatus.pr_reg.csr_badv =3D cpu_to_dump64(s, env->CSR_BADV); + ret =3D f(¬e, LOONGARCH_PRSTATUS_NOTE_SIZE, s); + if (ret < 0) { + return -1; + } + + ret =3D loongarch_write_elf64_fprpreg(f, env, cpuid, s); + if (ret < 0) { + return -1; + } + + return ret; +} + +int cpu_get_dump_info(ArchDumpInfo *info, + const GuestPhysBlockList *guest_phys_blocks) +{ + info->d_machine =3D EM_LOONGARCH; + info->d_endian =3D ELFDATA2LSB; + info->d_class =3D ELFCLASS64; + + return 0; +} + +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +{ + size_t note_size =3D 0; + + if (class =3D=3D ELFCLASS64) { + note_size =3D LOONGARCH_PRSTATUS_NOTE_SIZE + LOONGARCH_PRFPREG_NOT= E_SIZE; + } + + return note_size * nr_cpus; +} diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 6a569285b8..7212fb5f8f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -768,6 +768,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps loongarch_sysemu_ops =3D { + .write_elf64_note =3D loongarch_cpu_write_elf64_note, .get_phys_page_debug =3D loongarch_cpu_get_phys_page_debug, }; =20 diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 944153b180..1a02427627 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -72,5 +72,7 @@ void write_fcc(CPULoongArchState *env, uint64_t val); int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int= n); int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n= ); void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs); +int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, DumpState *s); =20 #endif diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build index e002e9aaf6..7817318287 100644 --- a/target/loongarch/meson.build +++ b/target/loongarch/meson.build @@ -8,6 +8,7 @@ loongarch_ss.add(files( =20 loongarch_system_ss =3D ss.source_set() loongarch_system_ss.add(files( + 'arch_dump.c', 'cpu_helper.c', 'loongarch-qmp-cmds.c', 'machine.c', --=20 2.34.1 From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146665076195.4875804620666; Thu, 12 Sep 2024 06:11:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZx-0003ut-2g; Thu, 12 Sep 2024 09:09:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZj-0003AA-QP for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZg-0004qA-Pj for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:31 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxC+oE6OJm7uQFAA--.13752S3; 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Donenfeld" , Bibo Mao Subject: [PULL 5/7] hw/loongarch: virt: support up to 4 serial ports Date: Thu, 12 Sep 2024 20:51:30 +0800 Message-Id: <20240912125132.268802-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S7 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146905264116600 Content-Type: text/plain; charset="utf-8" From: "Jason A. Donenfeld" In order to support additional channels of communication using `-serial`, add several serial ports, up to the standard 4 generally supported by the 8250 driver. Fixed: https://lore.kernel.org/all/20240907143439.2792924-1-Jason@zx2c4.com/ Signed-off-by: Jason A. Donenfeld Tested-by: Bibo Mao [gaosong: ACPI uart need't reverse order] Signed-off-by: Song Gao Message-Id: <20240907143439.2792924-1-Jason@zx2c4.com> --- hw/loongarch/acpi-build.c | 23 +++++++++++++++-------- hw/loongarch/virt.c | 27 +++++++++++++++++---------- include/hw/pci-host/ls7a.h | 9 +++++---- 3 files changed, 37 insertions(+), 22 deletions(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 2638f87434..04107c84ba 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -31,6 +31,7 @@ =20 #include "hw/acpi/generic_event_device.h" #include "hw/pci-host/gpex.h" +#include "sysemu/sysemu.h" #include "sysemu/tpm.h" #include "hw/platform-bus.h" #include "hw/acpi/aml-build.h" @@ -252,23 +253,27 @@ struct AcpiBuildState { MemoryRegion *linker_mr; } AcpiBuildState; =20 -static void build_uart_device_aml(Aml *table) +static void build_uart_device_aml(Aml *table, int index) { Aml *dev; Aml *crs; Aml *pkg0, *pkg1, *pkg2; - uint32_t uart_irq =3D VIRT_UART_IRQ; - - Aml *scope =3D aml_scope("_SB"); - dev =3D aml_device("COMA"); + Aml *scope; + uint32_t uart_irq; + uint64_t base; + + uart_irq =3D VIRT_UART_IRQ + index; + base =3D VIRT_UART_BASE + index * VIRT_UART_SIZE; + scope =3D aml_scope("_SB"); + dev =3D aml_device("COM%d", index); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(index))); aml_append(dev, aml_name_decl("_CCA", aml_int(1))); crs =3D aml_resource_template(); aml_append(crs, aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, VIRT_UART_BASE, VIRT_UART_BASE + VIRT_UART_SIZ= E - 1, + 0, base, base + VIRT_UART_SIZE - 1, 0, VIRT_UART_SIZE)); aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, AML_SHARED, &uart_irq, 1)); @@ -401,6 +406,7 @@ static void acpi_dsdt_add_tpm(Aml *scope, LoongArchVirt= MachineState *vms) static void build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) { + int i; Aml *dsdt, *scope, *pkg; LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(machine); AcpiTable table =3D { .sig =3D "DSDT", .rev =3D 1, .oem_id =3D lvms->o= em_id, @@ -408,7 +414,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Mach= ineState *machine) =20 acpi_table_begin(&table, table_data); dsdt =3D init_aml_allocator(); - build_uart_device_aml(dsdt); + for (i =3D 0; i < VIRT_UART_COUNT; i++) + build_uart_device_aml(dsdt, i); build_pci_device_aml(dsdt, lvms); build_la_ged_aml(dsdt, machine); build_flash_aml(dsdt, lvms); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 29040422aa..76dd29a391 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -280,10 +280,10 @@ static void fdt_add_rtc_node(LoongArchVirtMachineStat= e *lvms, } =20 static void fdt_add_uart_node(LoongArchVirtMachineState *lvms, - uint32_t *pch_pic_phandle) + uint32_t *pch_pic_phandle, hwaddr base, + int irq, bool chosen) { char *nodename; - hwaddr base =3D VIRT_UART_BASE; hwaddr size =3D VIRT_UART_SIZE; MachineState *ms =3D MACHINE(lvms); =20 @@ -292,9 +292,9 @@ static void fdt_add_uart_node(LoongArchVirtMachineState= *lvms, qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); - qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); - qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4); + if (chosen) + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodenam= e); + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4); qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", *pch_pic_phandle); g_free(nodename); @@ -706,11 +706,18 @@ static void virt_devices_init(DeviceState *pch_pic, /* Add pcie node */ fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle); =20 - serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, - qdev_get_gpio_in(pch_pic, - VIRT_UART_IRQ - VIRT_GSI_BASE), - 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); - fdt_add_uart_node(lvms, pch_pic_phandle); + /* + * Create uart fdt node in reverse order so that they appear + * in the finished device tree lowest address first + */ + for (i =3D VIRT_UART_COUNT; i --> 0;) { + hwaddr base =3D VIRT_UART_BASE + i * VIRT_UART_SIZE; + int irq =3D VIRT_UART_IRQ + i - VIRT_GSI_BASE; + serial_mm_init(get_system_memory(), base, 0, + qdev_get_gpio_in(pch_pic, irq), + 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); + fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i =3D=3D 0); + } =20 /* Network init */ pci_init_nic_devices(pci_bus, mc->default_nic); diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index cd7c9ec7bc..79d4ea8501 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -36,17 +36,18 @@ #define VIRT_PCH_PIC_IRQ_NUM 32 #define VIRT_GSI_BASE 64 #define VIRT_DEVICE_IRQS 16 +#define VIRT_UART_COUNT 4 #define VIRT_UART_IRQ (VIRT_GSI_BASE + 2) #define VIRT_UART_BASE 0x1fe001e0 -#define VIRT_UART_SIZE 0X100 -#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 3) +#define VIRT_UART_SIZE 0x100 +#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6) #define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000) #define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100) #define VIRT_RTC_LEN 0x100 -#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 4) +#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7) =20 #define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 #define VIRT_PLATFORM_BUS_SIZE 0x2000000 #define VIRT_PLATFORM_BUS_NUM_IRQS 2 -#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 5) +#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8) #endif --=20 2.34.1 From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146697860733.4140944016511; Thu, 12 Sep 2024 06:11:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZm-0003K9-GH; Thu, 12 Sep 2024 09:09:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZj-00039M-KB for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZg-0004q3-Qw for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:31 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxSOkE6OJm8eQFAA--.12716S3; Thu, 12 Sep 2024 21:09:24 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S8; Thu, 12 Sep 2024 21:09:24 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, "Jason A. Donenfeld" Subject: [PULL 6/7] hw/loongarch: virt: pass random seed to fdt Date: Thu, 12 Sep 2024 20:51:31 +0800 Message-Id: <20240912125132.268802-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146912421116600 Content-Type: text/plain; charset="utf-8" From: "Jason A. Donenfeld" If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to initialize early. Set this using the usual guest random number generation function. This is the same procedure that's done in b91b6b5a2c ("hw/microblaze: pass random seed to fdt"), e4b4f0b71c ("hw/riscv: virt: pass random seed to fdt"), c6fe3e6b4c ("hw/openrisc: virt: pass random seed to fdt"), 67f7e426e5 ("hw/i386: pass RNG seed via setup_data entry"), c287941a4d ("hw/rx: pass random seed to fdt"), 5e19cc68fb ("hw/mips: boston: pass random seed to fdt"), 6b23a67916 ("hw/nios2: virt: pass random seed to fdt") c4b075318e ("hw/ppc: pass random seed to fdt"), and 5242876f37 ("hw/arm/virt: dt: add rng-seed property"). These earlier commits later were amended to rerandomize the RNG seed on snapshot load, but the LoongArch code somehow already does that, despite not having this patch here, presumably due to some lucky copy and pasting. Signed-off-by: Jason A. Donenfeld Reviewed-by: Song Gao Message-Id: <20240905153316.2038769-1-Jason@zx2c4.com> Signed-off-by: Song Gao --- hw/loongarch/virt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 76dd29a391..81b1f9486f 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -48,6 +48,7 @@ #include "hw/block/flash.h" #include "hw/virtio/virtio-iommu.h" #include "qemu/error-report.h" +#include "qemu/guest-random.h" =20 static bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms) { @@ -303,6 +304,7 @@ static void fdt_add_uart_node(LoongArchVirtMachineState= *lvms, static void create_fdt(LoongArchVirtMachineState *lvms) { MachineState *ms =3D MACHINE(lvms); + uint8_t rng_seed[32]; =20 ms->fdt =3D create_device_tree(&lvms->fdt_size); if (!ms->fdt) { @@ -316,6 +318,10 @@ static void create_fdt(LoongArchVirtMachineState *lvms) qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); qemu_fdt_add_subnode(ms->fdt, "/chosen"); + + /* Pass seed to RNG */ + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); } =20 static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms) --=20 2.34.1 From nobody Sun Nov 24 03:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726146672683474.35542480773313; Thu, 12 Sep 2024 06:11:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZv-0003lh-Vw; Thu, 12 Sep 2024 09:09:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sojZj-00039Q-KW for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:31 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sojZg-0004qO-RG for qemu-devel@nongnu.org; Thu, 12 Sep 2024 09:09:31 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxB+kG6OJm9uQFAA--.12642S3; Thu, 12 Sep 2024 21:09:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMDxl8Xr5+JmR8MFAA--.9219S9; Thu, 12 Sep 2024 21:09:24 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Bibo Mao Subject: [PULL 7/7] hw/loongarch: Add acpi SPCR table support Date: Thu, 12 Sep 2024 20:51:32 +0800 Message-Id: <20240912125132.268802-8-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20240912125132.268802-1-gaosong@loongson.cn> References: <20240912125132.268802-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qciowMDxl8Xr5+JmR8MFAA--.9219S9 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1726146906625116600 Content-Type: text/plain; charset="utf-8" From: Bibo Mao Serial port console redirection table can be used for default serial port selection, like chosen stdout-path selection with FDT method. With acpi SPCR table added, early debug console can be parsed from SPCR table with simple kernel parameter earlycon rather than earlycon=3Duart,mmio,0x1fe001e0 Signed-off-by: Bibo Mao Reviewed-by: Song Gao Message-Id: <20240907073037.243353-1-maobibo@loongson.cn> Signed-off-by: Song Gao --- hw/loongarch/acpi-build.c | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 04107c84ba..50709bda0f 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -242,6 +242,44 @@ build_srat(GArray *table_data, BIOSLinker *linker, Mac= hineState *machine) acpi_table_end(linker, &table); } =20 +/* + * Serial Port Console Redirection Table (SPCR) + * https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/ser= ial-port-console-redirection-table + */ +static void +spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine) +{ + LoongArchVirtMachineState *lvms; + AcpiSpcrData serial =3D { + .interface_type =3D 0, /* 16550 compatible */ + .base_addr.id =3D AML_AS_SYSTEM_MEMORY, + .base_addr.width =3D 32, + .base_addr.offset =3D 0, + .base_addr.size =3D 1, + .base_addr.addr =3D VIRT_UART_BASE, + .interrupt_type =3D 0, /* Interrupt not supported */ + .pc_interrupt =3D 0, + .interrupt =3D VIRT_UART_IRQ, + .baud_rate =3D 7, /* 115200 */ + .parity =3D 0, + .stop_bits =3D 1, + .flow_control =3D 0, + .terminal_type =3D 3, /* ANSI */ + .language =3D 0, /* Language */ + .pci_device_id =3D 0xffff, /* not a PCI device*/ + .pci_vendor_id =3D 0xffff, /* not a PCI device*/ + .pci_bus =3D 0, + .pci_device =3D 0, + .pci_function =3D 0, + .pci_flags =3D 0, + .pci_segment =3D 0, + }; + + lvms =3D LOONGARCH_VIRT_MACHINE(machine); + build_spcr(table_data, linker, &serial, 2, lvms->oem_id, + lvms->oem_table_id); +} + typedef struct AcpiBuildState { /* Copy of table in RAM (for patching). */ @@ -484,6 +522,8 @@ static void acpi_build(AcpiBuildTables *tables, Machine= State *machine) =20 acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); + acpi_add_table(table_offsets, tables_blob); + spcr_setup(tables_blob, tables->linker, machine); =20 if (machine->numa_state->num_nodes) { if (machine->numa_state->have_numa_distance) { --=20 2.34.1