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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42caeb33a92sm165637475e9.20.2024.09.12.01.48.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Sep 2024 01:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726130920; x=1726735720; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Q7zUVA3YeImHTytYVuv09gAKlWA0rSKOT0ww4Ea2dk=; b=V+aMlYXnDAzUxbcJ1oAVAVmQF2HWA/BaoyKaG2zoCcSLI4LlrcRU36XyPYn3/813ck eD/tmk5wjnNrYTcH+c9bxomKk7oTMynivxqwoi2DheEjkaAv7JvB9kvPlneIbEa/6yyB zKnzJs+ESR9kEKIqUSrhWyA6kxZKO5xoFRqbuRlqWbWT2jlaAnM9/3iDBT5fm+nxFpdy bg0DECtHwhsAsFsN1fMvM9XcuCBRpzgNe71UqNv1D+e5BczCyUxkwZgLbN3fMWRBjx4v U4fPtQ63UeIDBcRjZAjqxOco9Ed14F+GmYwfcGSm4iI1ZVs9RANhphx6Jq85A6IRNHYe WaMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726130920; x=1726735720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Q7zUVA3YeImHTytYVuv09gAKlWA0rSKOT0ww4Ea2dk=; b=eRbyo/qErDp4Iff64GvY2OjEifgbjI08IaM54Zn5t7GPwAwizsSgM/GYCbY0jVw/O7 NyPtGh7aSe2AgzyvaCXZ1xJRsqVgm4ce9CywqAUffeWGWp6CfUyN1avSgoXbvrl91q/H FYMZIut3LVWLJpxpqAAuLAqskAHHbX3xorrPQZicfKhJ7elqfN6XWGECq0CoFT6NMiSt 305xjLMzsKmiAbaMiQYXMPo5JWaHzGYWgQJBlRRvv2F+6v4HV2Is4QTeFMPbFwswUTY0 OHARg6YaAIhuxNL4m/RZtZSc0LkXv5Vr2oV9n/615XUoZSVUULHBYoGkTZtwb4PLnTyN nc6Q== X-Forwarded-Encrypted: i=1; AJvYcCXqA4Mf1Z0qvDgGHpzlB13L5lqcgbrq6v5tpxcXSW9Vk8pHyv0K+hSCE8Ehu8UWOJigkUguxVw3YJLg@nongnu.org X-Gm-Message-State: AOJu0Yx2NkVDGhEdwYj0JOJNbW6YSO/dMWWiQrCNywc5fh/NWAXT23Os Eyn5t6jgwTrqsqxarGfhQJjhT2rOnAX3JNfDFVLZwHa81am35+HPtE28DXoRiIU= X-Google-Smtp-Source: AGHT+IHbcdULDcxn8lygJmAwebRCgNUdJEYYYfS2fYLbC9HqdQbd5IjXrMiTUjx1qmx+P37J1PAhuA== X-Received: by 2002:a05:600c:21d9:b0:42c:b1a4:c3ef with SMTP id 5b1f17b1804b1-42cdfb15de5mr6891695e9.33.1726130919405; Thu, 12 Sep 2024 01:48:39 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH 02/10] target/riscv: Add Ssdbltrp CSRs handling Date: Thu, 12 Sep 2024 10:48:21 +0200 Message-ID: <20240912084832.2906991-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240912084832.2906991-1-cleger@rivosinc.com> References: <20240912084832.2906991-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1726130998436116600 Implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 16 ++++++++++++++ target/riscv/csr.c | 45 ++++++++++++++++++++++++++++++--------- 4 files changed, 58 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a84e719d3f..ee984bf270 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -553,6 +553,7 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ul= ong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index da1723496c..3a5588d4df 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -558,6 +558,7 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ +#define MSTATUS_SDT 0x01000000 #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL =20 @@ -588,6 +589,7 @@ typedef enum { #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 +#define SSTATUS_SDT 0x01000000 =20 #define SSTATUS64_UXL 0x0000000300000000ULL =20 @@ -777,11 +779,13 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_DTE (1ULL << 59) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) =20 /* For RV32 */ +#define MENVCFGH_DTE BIT(27) #define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -795,11 +799,13 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_DTE MENVCFG_DTE #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE =20 /* For RV32 */ +#define HENVCFGH_DTE MENVCFGH_DTE #define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9d0400035f..395d8235ce 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -63,6 +63,22 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + if (!riscv_cpu_cfg(env)->ext_ssdbltrp) { + return false; + } + if (virt) { + return (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else { + return (env->menvcfg & MENVCFG_DTE) !=3D 0; + } +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e5de72453c..d8280ec956 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -540,6 +540,15 @@ static RISCVException aia_hmode32(CPURISCVState *env, = int csrno) return hmode32(env, csrno); } =20 +static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + return RISCV_EXCP_NONE; + } + + return hmode(env, csrno); +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { @@ -1402,7 +1411,7 @@ static const target_ulong vs_delegable_excps =3D DELE= GABLE_EXCPS & (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | SSTATUS_SDT; =20 /* * Spec allows for bits 13:63 to be either read-only or writable. @@ -1600,6 +1609,14 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, mask |=3D MSTATUS_VS; } =20 + if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) { + mask |=3D MSTATUS_SDT; + if ((val & MSTATUS_SDT) !=3D 0) { + mstatus &=3D ~MSTATUS_SIE; + val &=3D ~MSTATUS_SIE; + } + } + if (xl !=3D MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |=3D MSTATUS_MPV | MSTATUS_GVA; @@ -2354,7 +2371,8 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 @@ -2374,7 +2392,8 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); @@ -2425,9 +2444,10 @@ static RISCVException read_henvcfg(CPURISCVState *en= v, int csrno, * henvcfg.pbmte is read_only 0 when menvcfg.pbmte =3D 0 * henvcfg.stce is read_only 0 when menvcfg.stce =3D 0 * henvcfg.adue is read_only 0 when menvcfg.adue =3D 0 + * henvcfg.dte is read_only 0 when menvcfg.dte =3D 0 */ - *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ) | - env->menvcfg); + *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= | + HENVCFG_DTE) | env->menvcfg); return RISCV_EXCP_NONE; } =20 @@ -2435,6 +2455,7 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + uint64_t menvcfg_mask; RISCVException ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -2443,7 +2464,11 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE); + menvcfg_mask =3D HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE; + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + menvcfg_mask |=3D HENVCFG_DTE; + } + mask |=3D env->menvcfg & menvcfg_mask; } =20 env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); @@ -2461,8 +2486,8 @@ static RISCVException read_henvcfgh(CPURISCVState *en= v, int csrno, return ret; } =20 - *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E) | - env->menvcfg)) >> 32; + *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E | + HENVCFG_DTE) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } =20 @@ -2470,7 +2495,7 @@ static RISCVException write_henvcfgh(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_ADUE); + HENVCFG_ADUE | HENVCFG_DTE); uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; =20 @@ -5246,7 +5271,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_v= satp, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_m= tval2, + [CSR_MTVAL2] =3D { "mtval2", dbltrp_hmode, read_mtval2, write_mtv= al2, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_m= tinst, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, --=20 2.45.2