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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9e1dsm7513155ad.236.2024.09.11.22.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726119046; x=1726723846; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uuV1qEXFWDTUGqNLxwAHmkJmRuD0mHEgZ+QMPt9fcjE=; b=jGfix3qU/mAbEm5lVrbjWVDJhV6Lxk/nYKxiyZKBzdT/Imh3GiVyE5hatZoaVae9gX ikKBsDlHElAXMItgnAmZOelWWc/7YW3qF2iPkipC+6u43x6e+6ovpJWMYAq0rnHMt7H3 GXc9mGTE3fsovhTnFCsQi3qcqjVkZNzmYsfPGOf9QSmyHRL5McNkJc4Bz4wSiujvdRlJ u4QP2hEy5frD8fwluCMWw6YZsTSPruBrHNTKEcmlJU0mFMtSqA0IrSnAeBfmdUw8QmMv 2JfJG2goCAVvJBR94EpYmgMpcAmaM95E+7lPJfk0kPVkDlYkh+e6OOSHT/RxLx0szO1N vOOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726119046; x=1726723846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uuV1qEXFWDTUGqNLxwAHmkJmRuD0mHEgZ+QMPt9fcjE=; b=WSJ3gFSx79Fhi2kfTNQKOu3zfe6t67OMztUR7aBBXgVhz3Pb3hu65aG0v+sruSZGAb rXp+o9flFto9Ru5NvoNaYiuUNUZ2cqr/JS5auubeTzvnP/KDamYPdaRz0ZctPbwKbTEx 1zgqibXpuo0v3GXt2jczxv5yZCx7iFdbTmNwG9TKF02UrArchQMLY/hJiqqGLOBbV3uc OtgN1IeJVtM3dYnzBj8m+cieId/r2LqPo5qvkNWwWkWwj/LwlzqV+05RnCq7Y2NnaKvp EbIY+qvBe+ldK1+BLQzlEe/f5GDA3ZgdNgrLTfIlTZp9iLBJ6CZjcm2x6cfZh/8oyYBO lt8Q== X-Gm-Message-State: AOJu0YzGhDm0tMpao0WNc22CB+Wj6/zm9RCZ2FIRQm6Xir2V0NA7mOuX NBoVdX5z7iweqkAlTULhgy/fLKdycat0I6W4B94a4gMAznbefzg9eiuGJEGwfxJkAJZeWX3x3Ph 4 X-Google-Smtp-Source: AGHT+IFS0dKDSDhVNMG12D5nLySaDwQh3X/8CcNRsnpNS8Dnmwq0pPGF4LSipjOB6KmpZ2VZPRJ6rw== X-Received: by 2002:a17:902:d4c7:b0:205:5410:5738 with SMTP id d9443c01a7336-2076e3944aamr20199755ad.27.1726119045788; Wed, 11 Sep 2024 22:30:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Carl Hauser , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PULL 1/5] target/sparc: Add FQ and FSR.QNE Date: Wed, 11 Sep 2024 22:30:39 -0700 Message-ID: <20240912053043.1131626-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912053043.1131626-1-richard.henderson@linaro.org> References: <20240912053043.1131626-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726119938616116600 From: Carl Hauser Add support for, and migrate, a single-entry fp instruction queue for sparc32. Signed-off-by: Carl Hauser [rth: Split from a larger patch; adjust representation with union; add migration state] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Mark Cave-Ayland Tested-by: Carl Hauser --- target/sparc/cpu.h | 22 ++++++++++++++++++++++ target/sparc/fop_helper.c | 4 ++++ target/sparc/machine.c | 25 +++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index dfd9512a21..9f2bc44722 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -184,6 +184,8 @@ enum { #define FSR_FTT_SEQ_ERROR (4ULL << 14) #define FSR_FTT_INVAL_FPR (6ULL << 14) =20 +#define FSR_QNE (1ULL << 13) + #define FSR_FCC0_SHIFT 10 #define FSR_FCC1_SHIFT 32 #define FSR_FCC2_SHIFT 34 @@ -438,6 +440,26 @@ struct CPUArchState { uint32_t fsr_cexc_ftt; /* cexc, ftt */ uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ =20 +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + /* + * Single-element FPU fault queue, with address and insn, + * packaged into the double-word with which it is stored. + */ + uint32_t fsr_qne; /* qne */ + union { + uint64_t d; + struct { +#if HOST_BIG_ENDIAN + uint32_t addr; + uint32_t insn; +#else + uint32_t insn; + uint32_t addr; +#endif + } s; + } fq; +#endif + CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted from PSR) */ diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 0b30665b51..b6692382b3 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -545,6 +545,8 @@ target_ulong cpu_get_fsr(CPUSPARCState *env) fsr |=3D (uint64_t)env->fcc[1] << FSR_FCC1_SHIFT; fsr |=3D (uint64_t)env->fcc[2] << FSR_FCC2_SHIFT; fsr |=3D (uint64_t)env->fcc[3] << FSR_FCC3_SHIFT; +#elif !defined(CONFIG_USER_ONLY) + fsr |=3D env->fsr_qne; #endif =20 /* VER is kept completely separate until re-assembly. */ @@ -591,6 +593,8 @@ void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) env->fcc[1] =3D extract64(fsr, FSR_FCC1_SHIFT, 2); env->fcc[2] =3D extract64(fsr, FSR_FCC2_SHIFT, 2); env->fcc[3] =3D extract64(fsr, FSR_FCC3_SHIFT, 2); +#elif !defined(CONFIG_USER_ONLY) + env->fsr_qne =3D fsr & FSR_QNE; #endif =20 set_fsr_nonsplit(env, fsr); diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 48e0cf22f3..222e5709c5 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -143,6 +143,24 @@ static const VMStateInfo vmstate_xcc =3D { .get =3D get_xcc, .put =3D put_xcc, }; +#else +static bool fq_needed(void *opaque) +{ + SPARCCPU *cpu =3D opaque; + return cpu->env.fsr_qne; +} + +static const VMStateDescription vmstate_fq =3D { + .name =3D "cpu/fq", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D fq_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(env.fq.s.addr, SPARCCPU), + VMSTATE_UINT32(env.fq.s.insn, SPARCCPU), + VMSTATE_END_OF_LIST() + }, +}; #endif =20 static int cpu_pre_save(void *opaque) @@ -265,4 +283,11 @@ const VMStateDescription vmstate_sparc_cpu =3D { #endif VMSTATE_END_OF_LIST() }, +#ifndef TARGET_SPARC64 + .subsections =3D (const VMStateDescription * const []) { + &vmstate_fq, + NULL + }, +#endif + }; --=20 2.43.0