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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc8fdesm3833034b3a.1.2024.09.11.22.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726119095; x=1726723895; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OWRNqBOLFq4FyL64x5nOZ4nnL8+3dptfcD0f4BZvp8g=; b=FxNrfpRyyRUohmHnJel6/VdwdlecvR6yiA56tpJkeCOex1A94HWngyeVspf2TmXoeT LUs6g8nf8NFIeaqW5+c2YIS8tnVzOka/m7LLM+IR6NLHbOtJ/BjQVndeGj0zqgf3xaOg I5hNn1G34rkcbMRCIiOfO11bTCmTIIS3twb8ptc3gDV+vA1waDNJrhp2ddssCnEnl5Nc UYQnnunc5m9/w7Tr8mw7OshmWYtrFUO5aO7ADQ4X7nskZiBRqwx0WUIyPRVxmNe2stNZ Md/2uWZWzXDIJDyfpmjHsRknVc5OZYTUnD1n8IjeiKjNe59f82WSlSh9UOfG0Hscrxs+ sgyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726119095; x=1726723895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OWRNqBOLFq4FyL64x5nOZ4nnL8+3dptfcD0f4BZvp8g=; b=ta485MSiOMFoWXVeyoaISIHsWbRwB/iIWHcvd1ElfWJdXSFa+v72HmC2oQN5NpwXbC tZqFOtFavZeBJ+EQIjwgIue7flEf1pCGgeUyc9EoHdkhmFucxYU44XVe4cTn06fJUnGE KPFNRgy+URtcKg420idicdTx1lWojtSfYuLVqiTeOlBQNibWEsGGqI/rmdtLDwWsqnnd ZaJSkkxHZNou5CrqxrKCOkTnesB7FBE7fyYwyd/aLRtWwkOVvJaJB7NSsYhSo6lJlr9x tbXyncC7IHo3K0jfDq43fSAclaPdMtyJg5kSfgFqAyKWKSIAhWkkCpN5FV8HbyjvflZX STWw== X-Gm-Message-State: AOJu0Yze0FuJ4i1zfvp1vAc100hHAd1y3Buis4C0dg2/BtVeWK53i4f5 MYXW9kvERVZJhfy3OYCayIudEtv/cojsWrRiq4/aWxpQESzeZlEGtD+uEw== X-Google-Smtp-Source: AGHT+IEyDw/nz2T4O3EeoQBhyYl9xwnRvpNnUZy8+M+BrRtkthzZepjosIjEMfqZLbtJnlMLUP59WQ== X-Received: by 2002:a05:6a00:1a93:b0:718:d519:20de with SMTP id d2e1a72fcca58-7192608f698mr2278081b3a.13.1726119095107; Wed, 11 Sep 2024 22:31:35 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Mark Corbin , Ajeet Singh , Kyle Evans , Richard Henderson , Alistair Francis Subject: [PULL 30/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection Date: Thu, 12 Sep 2024 15:29:35 +1000 Message-ID: <20240912052953.2552501-31-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com> References: <20240912052953.2552501-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1726119711550116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-6-itachis@FreeBSD.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_= elf.h new file mode 100644 index 0000000000..4eb915e61e --- /dev/null +++ b/bsd-user/riscv/target_arch_elf.h @@ -0,0 +1,42 @@ +/* + * RISC-V ELF definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#define elf_check_arch(x) ((x) =3D=3D EM_RISCV) +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 +#define ELF_CLASS ELFCLASS64 + +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_RISCV + +#define ELF_HWCAP get_elf_hwcap() +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu =3D RISCV_CPU(thread_cpu); + + return cpu->env.misa_ext_mask; +} + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* TARGET_ARCH_ELF_H */ --=20 2.46.0