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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc8fdesm3833034b3a.1.2024.09.11.22.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726119085; x=1726723885; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E8kqQOO07s/lXe7azl0i3Zls58n2NpD50p6A7IulL6U=; b=mcSteSlBtObYMgffV1oXWh2Gbr1JQ18AAmmSIrbKjciqk/NOtUuLrhJwVVqcX0G/q3 ZGDndwxkoH9gjpZodkzBYBb25Ahy3/WmJCf7ckt3WEeO3opyMFeyzNewTDMtLPbFX7j6 qexc42TDQmZc5m+Q14q/htaFhkGNSNIGYzICgbsx+7LqW5GPk+Y6JSs++mNAGqjY6lak LNmDlhQeHH+Ti6GWMbKK7+39q44G3r2M52KVrpiv7TPudHv8hOBYGalavJtKHmwW3p79 8AaMQc5LWzVGISuHWVXHjSywUSAG9eZAsPwQNRek36qA8c38stYfEqpiJb3mHCjtwND8 kJ9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726119085; x=1726723885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E8kqQOO07s/lXe7azl0i3Zls58n2NpD50p6A7IulL6U=; b=iRr6PqEImgf10tzSSecpfcAsgySQggG6DQF8qNabqmSqxa4Q8OL2Da17p+Zfm9iYgQ dQo4K2141wvF8Ses02OHAr/WuFFrp970/BPNhAq3eUVwp+GzLOwhSd6U3WVMBvJi4a1S jyoC22RxHhw4POi0g2wWdRAuIS7ZuLpPVC9028LArPwSlCGpAM+3QF2hugPKzpM68vor i214KZ8mLOp2ZZ6qtryZxZbmN+KVEtxBCeZbEXy2zrU42vMrxl79zv0/KwRuBgqSqBXM LqDy0XbyYJvOQLQUen/zzbSNO5DjGwiGv6cKZGNn4Waj+WMqsPEOtULmubK+MqWXU89t wj+w== X-Gm-Message-State: AOJu0YzVX7X4zj5GTUZllNi5Gle9XBQ0AKFni+O8L+UUTSzfkS6yGWnJ rUYyL/jUSgtvi6Wx5BcBiFXwRQRePpBK1hSYkdcsywTOexIDCcXG4Ws+Pg== X-Google-Smtp-Source: AGHT+IGoECLeYMy/QdisTJx8qkw+47og9bgJWO/hw0VDS4uk/+zBn9afJ70lrMcTRJYqXX1cNPra7Q== X-Received: by 2002:a05:6a00:3e23:b0:717:8f0d:ec37 with SMTP id d2e1a72fcca58-71926206e36mr2172746b3a.25.1726119085088; Wed, 11 Sep 2024 22:31:25 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Mark Corbin , Ajeet Singh , Jessica Clarke , Kyle Evans , Richard Henderson , Alistair Francis Subject: [PULL 27/47] bsd-user: Add RISC-V CPU execution loop and syscall handling Date: Thu, 12 Sep 2024 15:29:32 +1000 Message-ID: <20240912052953.2552501-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com> References: <20240912052953.2552501-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1726119250841116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-3-itachis@FreeBSD.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h index e17c910ae9..ea2a8d1ace 100644 --- a/bsd-user/riscv/target_arch_cpu.h +++ b/bsd-user/riscv/target_arch_cpu.h @@ -36,4 +36,98 @@ static inline void target_cpu_init(CPURISCVState *env, env->pc =3D regs->sepc; } =20 +static inline void target_cpu_loop(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + int trapnr; + abi_long ret; + unsigned int syscall_num; + int32_t signo, code; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + signo =3D 0; + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + case RISCV_EXCP_U_ECALL: + syscall_num =3D env->gpr[xT0]; + env->pc +=3D TARGET_INSN_SIZE; + /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */ + if (TARGET_FREEBSD_NR___syscall =3D=3D syscall_num || + TARGET_FREEBSD_NR_syscall =3D=3D syscall_num) { + ret =3D do_freebsd_syscall(env, + env->gpr[xA0], + env->gpr[xA1], + env->gpr[xA2], + env->gpr[xA3], + env->gpr[xA4], + env->gpr[xA5], + env->gpr[xA6], + env->gpr[xA7], + 0); + } else { + ret =3D do_freebsd_syscall(env, + syscall_num, + env->gpr[xA0], + env->gpr[xA1], + env->gpr[xA2], + env->gpr[xA3], + env->gpr[xA4], + env->gpr[xA5], + env->gpr[xA6], + env->gpr[xA7] + ); + } + + /* + * Compare to cpu_set_syscall_retval() in + * riscv/riscv/vm_machdep.c + */ + if (ret >=3D 0) { + env->gpr[xA0] =3D ret; + env->gpr[xT0] =3D 0; + } else if (ret =3D=3D -TARGET_ERESTART) { + env->pc -=3D TARGET_INSN_SIZE; + } else if (ret !=3D -TARGET_EJUSTRETURN) { + env->gpr[xA0] =3D -ret; + env->gpr[xT0] =3D 1; + } + break; + case RISCV_EXCP_ILLEGAL_INST: + signo =3D TARGET_SIGILL; + code =3D TARGET_ILL_ILLOPC; + break; + case RISCV_EXCP_BREAKPOINT: + signo =3D TARGET_SIGTRAP; + code =3D TARGET_TRAP_BRKPT; + break; + case EXCP_DEBUG: + signo =3D TARGET_SIGTRAP; + code =3D TARGET_TRAP_BRKPT; + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception " + "0x%x - aborting\n", trapnr); + cpu_dump_state(cs, stderr, 0); + abort(); + } + + if (signo) { + force_sig_fault(signo, code, env->pc); + } + + process_pending_signals(env); + } +} + #endif /* TARGET_ARCH_CPU_H */ --=20 2.46.0