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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc8fdesm3833034b3a.1.2024.09.11.22.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:31:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726119081; x=1726723881; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YVK9TI3s4BFy65/tNanCHqrpz7AQul+OpsDeLsd5Jhg=; b=awS8w8Qmi6CP3FT//LU3xKRetvCH8LGhOFE+yNU5uz7y3SrTjbe3DNIGT773gK8p1w 2tPc1phPN+cQFC5q46qXMkYZBFbRjVC8IYq3hEhFZPEW5lMcsn7FNOpbT9U7DpP6kNVC PbgpY2hpv6+zZJf5VtLRh/m0R0DZyq+3q++GZUPi5HKhsPrD5kNJ3k+WUDXKGh10Z6fJ RzFUoOeyIvSMXT1kfOdE3OEIdSKC6FebVdxmbrEDb5XhcCGZVO9d4FUQ4pSoN0vMIyAY 1spf1g/JI2OokNJdS+kPTBIfr08fgJnn8rv6MKJPcRgcpLXUbzCNH5vzgtzsI4P2iKzY UdeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726119081; x=1726723881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YVK9TI3s4BFy65/tNanCHqrpz7AQul+OpsDeLsd5Jhg=; b=jdLdSj+l72cOuPcMVbuT/OjtTj9yqsHhID4I6npimpWQJ2ko9bRNhaHkpJ7c55JZju mFh1ujaAVmeq6PqvuUx/4CCE2L4BKZ9x83ZIOXoCFIj8PIHUGk/24Q6LFFLRP52njlm1 Hge6YOKpvyLML7DiBJTqCr20MG+HNJefvUq39DWjpWAtTs6HiJACd8KRpZYystUedEGY CACBlZccDeLg9KcSD8b1TTtYKFogAp3a1E+AVxpEw7zrphr6rREWNREkuKbC9UKeJLZz WYFGKpANMEqyoi2Hm/uBxbB8tul8E5la6lbrPCSuVz+321xMOrruLiBwGlzvt62tjUwU rPNw== X-Gm-Message-State: AOJu0Yyg3OJXbsXXWw3zDsjUXFEYNT4szxfuQrBRTH1Y9mLVtgPB2tOh kjW1G2F9c0jQ0xTYSaERJGmCf2nNPyJbSXDDm8I2m4xU4nBbZO78sWcoqw== X-Google-Smtp-Source: AGHT+IEVoM5te6rM3HJ2Ot5U9uDXTKZRhUfY6u7/I8ETDgpBHJkylQcM1KIW9fWM2EoX0A3mw73oTA== X-Received: by 2002:a05:6a00:1804:b0:70d:1dcf:e2b4 with SMTP id d2e1a72fcca58-71926059119mr2673129b3a.1.1726119081211; Wed, 11 Sep 2024 22:31:21 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Mark Corbin , Ajeet Singh , Jessica Clarke , Richard Henderson , Alistair Francis Subject: [PULL 26/47] bsd-user: Implement RISC-V CPU initialization and main loop Date: Thu, 12 Sep 2024 15:29:31 +1000 Message-ID: <20240912052953.2552501-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com> References: <20240912052953.2552501-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1726119976580116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20240907031927.1908-2-itachis@FreeBSD.org> Signed-off-by: Alistair Francis --- bsd-user/riscv/target_arch_cpu.h | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 bsd-user/riscv/target_arch_cpu.h diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h new file mode 100644 index 0000000000..e17c910ae9 --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.h @@ -0,0 +1,39 @@ +/* + * RISC-V CPU init and loop + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" + +#define TARGET_DEFAULT_CPU_MODEL "max" + +static inline void target_cpu_init(CPURISCVState *env, + struct target_pt_regs *regs) +{ + int i; + + for (i =3D 1; i < 32; i++) { + env->gpr[i] =3D regs->regs[i]; + } + + env->pc =3D regs->sepc; +} + +#endif /* TARGET_ARCH_CPU_H */ --=20 2.46.0