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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc8fdesm3833034b3a.1.2024.09.11.22.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 22:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726119065; x=1726723865; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D8IzRrTG3yIv5J3skaJtLVawEmGkxz4syszpjSziKs0=; b=fFV5VEZPbNDpG1qCy477Wp1XjDS7j4UqCYUzRYlyrBOWErwUJksL/dWBLGiughQK6L LsjFRVXgXQNQvYmlF2ORlpk1pihFLp99TGvtYta9BfhtY9lXxrNxAP+1sg45mJBR0Bho /mFGjsJsrCnAzXzvbuKbXCWT8UQ7zsyEbmILBTt33TGhkm3v+QEu9EAIYB90XKJnXVaV OF0M23U34tlXcffq9C9E53QfGw6Sfvnlq9gOD9RfC1lXjCemmrkwvL+ia0+PVtyTkcvd JN7hBfI/wnXxbb5NyRcXZ/Be8yMaX5WKnQYrzvamJwijQFhxLqcVsWhzR7cqO7GmVr8P wvbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726119065; x=1726723865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D8IzRrTG3yIv5J3skaJtLVawEmGkxz4syszpjSziKs0=; b=dmNT1TKa8uEXjmHWB+OdVlCLd62Twnu7xuBtqWWfT3ZYX68owetd2arVMFWJnsV07f 2BIeQLRv/hiNAB6gnxfFc7Qq34OjKtz0FVmQdOedpChtmQiO3twxkRPNK2SQYBiZ4ADL c07X7A8EKG96jYYzJL1/kY5y2WwHJNTlM92212InwImN+U9yrhws6mcmNTOESbWQzgZh Thsh23WI7d+aZkstjkib0qj+56ADWvNL+cxWDYRlWGIwi+bLx658BIQqxZwjFroalLUW xqOeWoQE2J+s38eYlCNk3qn1pKquNfQ17rI7cdFhZeLL7qq+Z8t3G4kSibEOC83B6Umf Ilsw== X-Gm-Message-State: AOJu0YxwWF3CVfJJRKLUiUS3KSoREsJhNzzR3BpIcDWv/+yyM+t5kebU z8edhNyQtfw8JQDwWmA0MISXOiW6llZdERzJV4YlTX9BNnYDyKInKzBQcg== X-Google-Smtp-Source: AGHT+IGbPrZSDWYu2nWp0p40I1Msos7p6oUFllizKHw80k9Dn/Wn1H1ofnl77s12PxJqSmzpu/9Sfg== X-Received: by 2002:a05:6a21:3942:b0:1cf:4326:5602 with SMTP id adf61e73a8af0-1cf761f9b30mr2103201637.36.1726119065413; Wed, 11 Sep 2024 22:31:05 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tomasz Jeznach , Daniel Henrique Barboza , Frank Chang , Alistair Francis Subject: [PULL 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Date: Thu, 12 Sep 2024 15:29:26 +1000 Message-ID: <20240912052953.2552501-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com> References: <20240912052953.2552501-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1726119938737116600 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage elements, although we don't support it yet. We'll introduce them next. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang Acked-by: Alistair Francis Message-ID: <20240903201633.93182-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.h | 3 + hw/riscv/riscv-iommu.c | 205 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 204 insertions(+), 4 deletions(-) diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index 95b4ce8d50..ddf5d50cf9 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -72,6 +72,9 @@ struct RISCVIOMMUState { =20 GHashTable *ctx_cache; /* Device translation Context Cache */ QemuMutex ctx_lock; /* Device translation Cache update lock */ + GHashTable *iot_cache; /* IO Translated Address Cache */ + QemuMutex iot_lock; /* IO TLB Cache update lock */ + unsigned iot_limit; /* IO Translation Cache size limit */ =20 /* MMIO Hardware Interface */ MemoryRegion regs_mr; diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 061a5efe19..fe81072b1c 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -65,6 +65,16 @@ struct RISCVIOMMUContext { uint64_t msiptp; /* MSI redirection page table pointer */ }; =20 +/* Address translation cache entry */ +struct RISCVIOMMUEntry { + uint64_t iova:44; /* IOVA Page Number */ + uint64_t pscid:20; /* Process Soft-Context identifier */ + uint64_t phys:44; /* Physical Page Number */ + uint64_t gscid:16; /* Guest Soft-Context identifier */ + uint64_t perm:2; /* IOMMU_RW flags */ + uint64_t __rfu:2; +}; + /* IOMMU index for transactions without process_id specified. */ #define RISCV_IOMMU_NOPROCID 0 =20 @@ -1156,13 +1166,130 @@ static AddressSpace *riscv_iommu_space(RISCVIOMMUS= tate *s, uint32_t devid) return &as->iova_as; } =20 +/* Translation Object cache support */ +static gboolean __iot_equal(gconstpointer v1, gconstpointer v2) +{ + RISCVIOMMUEntry *t1 =3D (RISCVIOMMUEntry *) v1; + RISCVIOMMUEntry *t2 =3D (RISCVIOMMUEntry *) v2; + return t1->gscid =3D=3D t2->gscid && t1->pscid =3D=3D t2->pscid && + t1->iova =3D=3D t2->iova; +} + +static guint __iot_hash(gconstpointer v) +{ + RISCVIOMMUEntry *t =3D (RISCVIOMMUEntry *) v; + return (guint)t->iova; +} + +/* GV: 1 PSCV: 1 AV: 1 */ +static void __iot_inval_pscid_iova(gpointer key, gpointer value, gpointer = data) +{ + RISCVIOMMUEntry *iot =3D (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg =3D (RISCVIOMMUEntry *) data; + if (iot->gscid =3D=3D arg->gscid && + iot->pscid =3D=3D arg->pscid && + iot->iova =3D=3D arg->iova) { + iot->perm =3D IOMMU_NONE; + } +} + +/* GV: 1 PSCV: 1 AV: 0 */ +static void __iot_inval_pscid(gpointer key, gpointer value, gpointer data) +{ + RISCVIOMMUEntry *iot =3D (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg =3D (RISCVIOMMUEntry *) data; + if (iot->gscid =3D=3D arg->gscid && + iot->pscid =3D=3D arg->pscid) { + iot->perm =3D IOMMU_NONE; + } +} + +/* GV: 1 GVMA: 1 */ +static void __iot_inval_gscid_gpa(gpointer key, gpointer value, gpointer d= ata) +{ + RISCVIOMMUEntry *iot =3D (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg =3D (RISCVIOMMUEntry *) data; + if (iot->gscid =3D=3D arg->gscid) { + /* simplified cache, no GPA matching */ + iot->perm =3D IOMMU_NONE; + } +} + +/* GV: 1 GVMA: 0 */ +static void __iot_inval_gscid(gpointer key, gpointer value, gpointer data) +{ + RISCVIOMMUEntry *iot =3D (RISCVIOMMUEntry *) value; + RISCVIOMMUEntry *arg =3D (RISCVIOMMUEntry *) data; + if (iot->gscid =3D=3D arg->gscid) { + iot->perm =3D IOMMU_NONE; + } +} + +/* GV: 0 */ +static void __iot_inval_all(gpointer key, gpointer value, gpointer data) +{ + RISCVIOMMUEntry *iot =3D (RISCVIOMMUEntry *) value; + iot->perm =3D IOMMU_NONE; +} + +/* caller should keep ref-count for iot_cache object */ +static RISCVIOMMUEntry *riscv_iommu_iot_lookup(RISCVIOMMUContext *ctx, + GHashTable *iot_cache, hwaddr iova) +{ + RISCVIOMMUEntry key =3D { + .gscid =3D get_field(ctx->gatp, RISCV_IOMMU_DC_IOHGATP_GSCID), + .pscid =3D get_field(ctx->ta, RISCV_IOMMU_DC_TA_PSCID), + .iova =3D PPN_DOWN(iova), + }; + return g_hash_table_lookup(iot_cache, &key); +} + +/* caller should keep ref-count for iot_cache object */ +static void riscv_iommu_iot_update(RISCVIOMMUState *s, + GHashTable *iot_cache, RISCVIOMMUEntry *iot) +{ + if (!s->iot_limit) { + return; + } + + qemu_mutex_lock(&s->iot_lock); + if (g_hash_table_size(s->iot_cache) >=3D s->iot_limit) { + iot_cache =3D g_hash_table_new_full(__iot_hash, __iot_equal, + g_free, NULL); + g_hash_table_unref(qatomic_xchg(&s->iot_cache, iot_cache)); + } + g_hash_table_add(iot_cache, iot); + qemu_mutex_unlock(&s->iot_lock); +} + +static void riscv_iommu_iot_inval(RISCVIOMMUState *s, GHFunc func, + uint32_t gscid, uint32_t pscid, hwaddr iova) +{ + GHashTable *iot_cache; + RISCVIOMMUEntry key =3D { + .gscid =3D gscid, + .pscid =3D pscid, + .iova =3D PPN_DOWN(iova), + }; + + iot_cache =3D g_hash_table_ref(s->iot_cache); + qemu_mutex_lock(&s->iot_lock); + g_hash_table_foreach(iot_cache, func, &key); + qemu_mutex_unlock(&s->iot_lock); + g_hash_table_unref(iot_cache); +} + static int riscv_iommu_translate(RISCVIOMMUState *s, RISCVIOMMUContext *ct= x, - IOMMUTLBEntry *iotlb) + IOMMUTLBEntry *iotlb, bool enable_cache) { + RISCVIOMMUEntry *iot; + IOMMUAccessFlags perm; bool enable_pid; bool enable_pri; + GHashTable *iot_cache; int fault; =20 + iot_cache =3D g_hash_table_ref(s->iot_cache); /* * TC[32] is reserved for custom extensions, used here to temporarily * enable automatic page-request generation for ATS queries. @@ -1170,9 +1297,45 @@ static int riscv_iommu_translate(RISCVIOMMUState *s,= RISCVIOMMUContext *ctx, enable_pri =3D (iotlb->perm =3D=3D IOMMU_NONE) && (ctx->tc & BIT_ULL(3= 2)); enable_pid =3D (ctx->tc & RISCV_IOMMU_DC_TC_PDTV); =20 + qemu_mutex_lock(&s->iot_lock); + iot =3D riscv_iommu_iot_lookup(ctx, iot_cache, iotlb->iova); + qemu_mutex_unlock(&s->iot_lock); + perm =3D iot ? iot->perm : IOMMU_NONE; + if (perm !=3D IOMMU_NONE) { + iotlb->translated_addr =3D PPN_PHYS(iot->phys); + iotlb->addr_mask =3D ~TARGET_PAGE_MASK; + iotlb->perm =3D perm; + fault =3D 0; + goto done; + } + /* Translate using device directory / page table information. */ fault =3D riscv_iommu_spa_fetch(s, ctx, iotlb); =20 + if (!fault && iotlb->target_as =3D=3D &s->trap_as) { + /* Do not cache trapped MSI translations */ + goto done; + } + + /* + * We made an implementation choice to not cache identity-mapped + * translations, as allowed by the specification, to avoid + * translation cache evictions for other devices sharing the + * IOMMU hardware model. + */ + if (!fault && iotlb->translated_addr !=3D iotlb->iova && enable_cache)= { + iot =3D g_new0(RISCVIOMMUEntry, 1); + iot->iova =3D PPN_DOWN(iotlb->iova); + iot->phys =3D PPN_DOWN(iotlb->translated_addr); + iot->gscid =3D get_field(ctx->gatp, RISCV_IOMMU_DC_IOHGATP_GSCID); + iot->pscid =3D get_field(ctx->ta, RISCV_IOMMU_DC_TA_PSCID); + iot->perm =3D iotlb->perm; + riscv_iommu_iot_update(s, iot_cache, iot); + } + +done: + g_hash_table_unref(iot_cache); + if (enable_pri && fault) { struct riscv_iommu_pq_record pr =3D {0}; if (enable_pid) { @@ -1312,13 +1475,40 @@ static void riscv_iommu_process_cq_tail(RISCVIOMMUS= tate *s) if (cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_PSCV) { /* illegal command arguments IOTINVAL.GVMA & PSCV =3D=3D 1= */ goto cmd_ill; + } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_GV)) { + /* invalidate all cache mappings */ + func =3D __iot_inval_all; + } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_AV)) { + /* invalidate cache matching GSCID */ + func =3D __iot_inval_gscid; + } else { + /* invalidate cache matching GSCID and ADDR (GPA) */ + func =3D __iot_inval_gscid_gpa; } - /* translation cache not implemented yet */ + riscv_iommu_iot_inval(s, func, + get_field(cmd.dword0, RISCV_IOMMU_CMD_IOTINVAL_GSCID), 0, + cmd.dword1 & TARGET_PAGE_MASK); break; =20 case RISCV_IOMMU_CMD(RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA, RISCV_IOMMU_CMD_IOTINVAL_OPCODE): - /* translation cache not implemented yet */ + if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_GV)) { + /* invalidate all cache mappings, simplified model */ + func =3D __iot_inval_all; + } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_PSCV)) { + /* invalidate cache matching GSCID, simplified model */ + func =3D __iot_inval_gscid; + } else if (!(cmd.dword0 & RISCV_IOMMU_CMD_IOTINVAL_AV)) { + /* invalidate cache matching GSCID and PSCID */ + func =3D __iot_inval_pscid; + } else { + /* invalidate cache matching GSCID and PSCID and ADDR (IOV= A) */ + func =3D __iot_inval_pscid_iova; + } + riscv_iommu_iot_inval(s, func, + get_field(cmd.dword0, RISCV_IOMMU_CMD_IOTINVAL_GSCID), + get_field(cmd.dword0, RISCV_IOMMU_CMD_IOTINVAL_PSCID), + cmd.dword1 & TARGET_PAGE_MASK); break; =20 case RISCV_IOMMU_CMD(RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT, @@ -1857,6 +2047,10 @@ static void riscv_iommu_realize(DeviceState *dev, Er= ror **errp) g_free, NULL); qemu_mutex_init(&s->ctx_lock); =20 + s->iot_cache =3D g_hash_table_new_full(__iot_hash, __iot_equal, + g_free, NULL); + qemu_mutex_init(&s->iot_lock); + s->iommus.le_next =3D NULL; s->iommus.le_prev =3D NULL; QLIST_INIT(&s->spaces); @@ -1869,6 +2063,7 @@ static void riscv_iommu_unrealize(DeviceState *dev) RISCVIOMMUState *s =3D RISCV_IOMMU(dev); =20 qemu_mutex_destroy(&s->core_lock); + g_hash_table_unref(s->iot_cache); g_hash_table_unref(s->ctx_cache); } =20 @@ -1876,6 +2071,8 @@ static Property riscv_iommu_properties[] =3D { DEFINE_PROP_UINT32("version", RISCVIOMMUState, version, RISCV_IOMMU_SPEC_DOT_VER), DEFINE_PROP_UINT32("bus", RISCVIOMMUState, bus, 0x0), + DEFINE_PROP_UINT32("ioatc-limit", RISCVIOMMUState, iot_limit, + LIMIT_CACHE_IOT), DEFINE_PROP_BOOL("intremap", RISCVIOMMUState, enable_msi, TRUE), DEFINE_PROP_BOOL("off", RISCVIOMMUState, enable_off, TRUE), DEFINE_PROP_BOOL("s-stage", RISCVIOMMUState, enable_s_stage, TRUE), @@ -1930,7 +2127,7 @@ static IOMMUTLBEntry riscv_iommu_memory_region_transl= ate( /* Translation disabled or invalid. */ iotlb.addr_mask =3D 0; iotlb.perm =3D IOMMU_NONE; - } else if (riscv_iommu_translate(as->iommu, ctx, &iotlb)) { + } else if (riscv_iommu_translate(as->iommu, ctx, &iotlb, true)) { /* Translation disabled or fault reported. */ iotlb.addr_mask =3D 0; iotlb.perm =3D IOMMU_NONE; --=20 2.46.0