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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108898; x=1726713698; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kgeom0orQyCoH8W6cLgDwpuRJ/jfJeEw1kOvWE0iihw=; b=VQtZFxpWO9opRNB1G3S24IdqqTINqfeveEeQ7SX8kb9vKDiu3qKBF2pEJXOHVWoGz6 APaQpD2TUAIOenrcaGNMg+RiMlut8Uw2J3o+0VZNB9ptiyZupGYb9Mwl5PWHPbxuMU7E 6+j4elNmxquLis9UJdFdb3uZeBxzTInsfK5ggw3c7EYlcAbSiP93ZTx94aodkoRzvTI+ Geol5KlNXOgHNvsfKHWQgSj7pj0Lo1iPSpjTd0KG6NjgfjLWXOjtV8lnrgoVAc/QdY2+ MZZnFlsdNn7gwI6Y0+w/jxXxQuo0bkMy51wcPcz3Xqq4LsCNJ3Xo3YolvoDVxRvBEf/8 lwOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108898; x=1726713698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kgeom0orQyCoH8W6cLgDwpuRJ/jfJeEw1kOvWE0iihw=; b=DB/SgOinEJqoK89Aqu4vS9pKJ8xBVYRKRmj4IyHwemKZJzX+H102aO8ETAnLBmOZ+H xOdvTxazZFB4n+SdcDKPNBCz9tDOUXxjsoDzdO3sSTF4P4eRyNOe1MK92mmsjw6LYiDt wrL6uMspboKnir+Cib4JNSRgoM8oZnFCQnzdVKF0hoPrTwqxpzNhwZsiMjpkFQRWaXbm wn4LzTfdpi4C40o73abhnkNAamhf6rjXxr8Y2ABdH+/ROMDaHv+9+92uJ3jCLniQX1rw F4LaPB/fl22mf6KoCq6e5jAMaXRfTAyVK30kj1NswwZ61aGv8U3PwZqhIKtZS8JnrLAH 9iJA== X-Gm-Message-State: AOJu0Yz+KWGwmwU+IGrApAXoyiXO5E2+hcDW9QVZFcZOfpxYDzDKf7Ly 8+45q5R+SpOzjDDBXnh7BrvEmBQOPDnONNvVDPhCr1jHvSygfGJMuHDDM+7KFki8CEWShWRRAZp Z X-Google-Smtp-Source: AGHT+IEgIQUB9SlaWeDya2oI07UQHB7jNQQMVwdvNVX/8VNf9n+6CUfGLG+kKVwNvmL4ls0E5JKVhw== X-Received: by 2002:a17:903:41cb:b0:206:ae39:9f4 with SMTP id d9443c01a7336-2076e35ebfamr15947455ad.20.1726108897922; Wed, 11 Sep 2024 19:41:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 24/29] target/arm: Convert handle_scalar_simd_shli to decodetree Date: Wed, 11 Sep 2024 19:41:09 -0700 Message-ID: <20240912024114.1097832-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109071191116600 Content-Type: text/plain; charset="utf-8" This includes SHL and SLI. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 +++++++--------------------------- target/arm/tcg/a64.decode | 4 ++++ 2 files changed, 13 insertions(+), 35 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index efd93a7f23..934746d2f2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7124,6 +7124,11 @@ static void gen_sri_d(TCGv_i64 dst, TCGv_i64 src, in= t64_t shift) } } =20 +static void gen_sli_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + tcg_gen_deposit_i64(dst, dst, src, shift, 64 - shift); +} + static bool do_vec_shift_imm_narrow(DisasContext *s, arg_qrri_e *a, WideShiftImmFn * const fns[3], MemOp s= ign) { @@ -7201,6 +7206,9 @@ TRANS(SRSRA_s, do_scalar_shift_imm, a, gen_srsra_d, t= rue, 0) TRANS(URSRA_s, do_scalar_shift_imm, a, gen_ursra_d, true, 0) TRANS(SRI_s, do_scalar_shift_imm, a, gen_sri_d, true, 0) =20 +TRANS(SHL_s, do_scalar_shift_imm, a, tcg_gen_shli_i64, false, 0) +TRANS(SLI_s, do_scalar_shift_imm, a, gen_sli_d, true, 0) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9417,38 +9425,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res= , TCGv_i64 tcg_src, } } =20 -/* SHL/SLI - Scalar shift left */ -static void handle_scalar_simd_shli(DisasContext *s, bool insert, - int immh, int immb, int opcode, - int rn, int rd) -{ - int size =3D 32 - clz32(immh) - 1; - int immhb =3D immh << 3 | immb; - int shift =3D immhb - (8 << size); - TCGv_i64 tcg_rn; - TCGv_i64 tcg_rd; - - if (!extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - tcg_rn =3D read_fp_dreg(s, rn); - tcg_rd =3D insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); - - if (insert) { - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); - } else { - tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); - } - - write_fp_dreg(s, rd, tcg_rd); -} - /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with * (signed/unsigned) narrowing */ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool i= s_q, @@ -9900,9 +9876,6 @@ static void disas_simd_scalar_shift_imm(DisasContext = *s, uint32_t insn) } =20 switch (opcode) { - case 0x0a: /* SHL / SLI */ - handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); - break; case 0x1c: /* SCVTF, UCVTF */ handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, opcode, rn, rd); @@ -9940,6 +9913,7 @@ static void disas_simd_scalar_shift_imm(DisasContext = *s, uint32_t insn) case 0x04: /* SRSHR / URSHR */ case 0x06: /* SRSRA / URSRA */ case 0x08: /* SRI */ + case 0x0a: /* SHL / SLI */ unallocated_encoding(s); break; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 6c2362b3bb..96803fe6e4 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1291,6 +1291,7 @@ RSHRN_v 0.00 11110 .... ... 10001 1 ..... ...= .. @q_shri_s =20 @shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ &rri_e esz=3D3 imm=3D%neon_rshift_i6 +@shli_d .... ..... 1 imm:6 ..... . rn:5 rd:5 &rri_e esz=3D3=20 =20 SSHR_s 0101 11110 .... ... 00000 1 ..... ..... @shri_d USHR_s 0111 11110 .... ... 00000 1 ..... ..... @shri_d @@ -1301,3 +1302,6 @@ URSHR_s 0111 11110 .... ... 00100 1 ..... ...= .. @shri_d SRSRA_s 0101 11110 .... ... 00110 1 ..... ..... @shri_d URSRA_s 0111 11110 .... ... 00110 1 ..... ..... @shri_d SRI_s 0111 11110 .... ... 01000 1 ..... ..... @shri_d + +SHL_s 0101 11110 .... ... 01010 1 ..... ..... @shli_d +SLI_s 0111 11110 .... ... 01010 1 ..... ..... @shli_d --=20 2.43.0