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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108897; x=1726713697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8xeiwUHFVZW2oDMUKIdwXlsFGkOBW4OXICqeXY8hybQ=; b=W/dFbiPyvXJ65T5Rxv6a5RF5HYhbV+RG+lKuARRqCI4t/tW7HnypJgjbGEIoiDCKtD ahv78mlhSeLrezyodSeKPkybLuZNUGRLRp9yTRw8JbdiI1fvz+9p3G/do4TmScuEUr6W hHbXvG09nxLC78XCjICTEC+Wh13I99uxwtoteIKQnsOUG6oI6cDlXKjhqTH+4btXlV7F zpDtGvIE2vNENtRjgMn6BRrMoGYQPEJkrNvC4doxdLDAxE4BpqKWwFOu/gnjlLZxQbWu gCP7pkmN+NSA7qM0LcP8PAqItYJ3GfCobDrpSb81kXxGrMT9EvassOgfoUlIk/buFeAb G8yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108897; x=1726713697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xeiwUHFVZW2oDMUKIdwXlsFGkOBW4OXICqeXY8hybQ=; b=Gp76/FfYiR1F0e6jj0JpDgzogUMgxD0KJOSCkIErF9fFHO0ydIYpwbyjMxnn0cmwWo Umqp3xX+THWfDScEGfDzVIvWQ4UAF4laXk/O8MEuq4cqYP+F+ShZeY/Cn+UefXiUIDib YfrCp4aIiZbRcGSxRbS1BvOBv3J/yf++oj5mZI7QWArwbTU2tbFIbZ/OtnOrNEFc49AH y0bcvj+nNBXtIuTvSYKs8CB4ruCJxjaP0wHxM3AXG5P7DPK3JQ6cW8Xry5f9PTgSdbHQ Bg2ZGGW21h5P9TxvPJX+hFN1tuSgTO4oAC4mHY6GcHG8sSoBUDCuYuAdLUd8BrN4tm9F x3rg== X-Gm-Message-State: AOJu0Yy5PgVicdfUStXa6ulglV+pjKfSP+Wru+nwu569Lw1oGUerrzXc ow3UtGmzFqvTLTNDKiG74a22asJJC/r8nSoYAxLztxAVYgThF3PQeeEoJ9nciNDu3d+zhOO/Gdt l X-Google-Smtp-Source: AGHT+IGqp8UYi6RgUedxZhHxfJ5FSLns3bWV0aJaQWbJsQXc4f5G9f4tnGmxVRLwwQCyexOg2oxR5Q== X-Received: by 2002:a17:902:db05:b0:206:c12d:abad with SMTP id d9443c01a7336-2076e393e31mr24548035ad.34.1726108897119; Wed, 11 Sep 2024 19:41:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 23/29] target/arm: Convert handle_scalar_simd_shri to decodetree Date: Wed, 11 Sep 2024 19:41:08 -0700 Message-ID: <20240912024114.1097832-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109103413116600 Content-Type: text/plain; charset="utf-8" This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 140 ++++++++++++++++----------------- target/arm/tcg/a64.decode | 16 ++++ 2 files changed, 86 insertions(+), 70 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8871087af0..efd93a7f23 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7035,6 +7035,18 @@ static void gen_ushr_d(TCGv_i64 dst, TCGv_i64 src, i= nt64_t shift) } } =20 +static void gen_ssra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_sshr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + +static void gen_usra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_ushr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + static void gen_srshr_bhs(TCGv_i64 dst, TCGv_i64 src, int64_t shift) { assert(shift >=3D 0 && shift <=3D 32); @@ -7091,6 +7103,27 @@ static void gen_urshr_d(TCGv_i64 dst, TCGv_i64 src, = int64_t shift) } } =20 +static void gen_srsra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_srshr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + +static void gen_ursra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_urshr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + +static void gen_sri_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + /* If shift is 64, dst is unchanged. */ + if (shift !=3D 64) { + tcg_gen_shri_i64(src, src, shift); + tcg_gen_deposit_i64(dst, dst, src, 0, 64 - shift); + } +} + static bool do_vec_shift_imm_narrow(DisasContext *s, arg_qrri_e *a, WideShiftImmFn * const fns[3], MemOp s= ign) { @@ -7136,6 +7169,38 @@ static WideShiftImmFn * const rshrn_fns[] =3D { }; TRANS(RSHRN_v, do_vec_shift_imm_narrow, a, rshrn_fns, 0) =20 +/* + * Advanced SIMD Scalar Shift by Immediate + */ + +static bool do_scalar_shift_imm(DisasContext *s, arg_rri_e *a, + WideShiftImmFn *fn, bool accumulate, + MemOp sign) +{ + if (fp_access_check(s)) { + TCGv_i64 rd =3D tcg_temp_new_i64(); + TCGv_i64 rn =3D tcg_temp_new_i64(); + + read_vec_element(s, rn, a->rn, 0, a->esz | sign); + if (accumulate) { + read_vec_element(s, rd, a->rd, 0, a->esz | sign); + } + fn(rd, rn, a->imm); + write_fp_dreg(s, a->rd, rd); + } + return true; +} + +TRANS(SSHR_s, do_scalar_shift_imm, a, gen_sshr_d, false, 0) +TRANS(USHR_s, do_scalar_shift_imm, a, gen_ushr_d, false, 0) +TRANS(SSRA_s, do_scalar_shift_imm, a, gen_ssra_d, true, 0) +TRANS(USRA_s, do_scalar_shift_imm, a, gen_usra_d, true, 0) +TRANS(SRSHR_s, do_scalar_shift_imm, a, gen_srshr_d, false, 0) +TRANS(URSHR_s, do_scalar_shift_imm, a, gen_urshr_d, false, 0) +TRANS(SRSRA_s, do_scalar_shift_imm, a, gen_srsra_d, true, 0) +TRANS(URSRA_s, do_scalar_shift_imm, a, gen_ursra_d, true, 0) +TRANS(SRI_s, do_scalar_shift_imm, a, gen_sri_d, true, 0) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9352,64 +9417,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res= , TCGv_i64 tcg_src, } } =20 -/* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ -static void handle_scalar_simd_shri(DisasContext *s, - bool is_u, int immh, int immb, - int opcode, int rn, int rd) -{ - const int size =3D 3; - int immhb =3D immh << 3 | immb; - int shift =3D 2 * (8 << size) - immhb; - bool accumulate =3D false; - bool round =3D false; - bool insert =3D false; - TCGv_i64 tcg_rn; - TCGv_i64 tcg_rd; - - if (!extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - switch (opcode) { - case 0x02: /* SSRA / USRA (accumulate) */ - accumulate =3D true; - break; - case 0x04: /* SRSHR / URSHR (rounding) */ - round =3D true; - break; - case 0x06: /* SRSRA / URSRA (accum + rounding) */ - accumulate =3D round =3D true; - break; - case 0x08: /* SRI */ - insert =3D true; - break; - } - - tcg_rn =3D read_fp_dreg(s, rn); - tcg_rd =3D (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new= _i64(); - - if (insert) { - /* shift count same as element size is valid but does nothing; - * special case to avoid potential shift by 64. - */ - int esize =3D 8 << size; - if (shift !=3D esize) { - tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); - } - } else { - handle_shri_with_rndacc(tcg_rd, tcg_rn, round, - accumulate, is_u, size, shift); - } - - write_fp_dreg(s, rd, tcg_rd); -} - /* SHL/SLI - Scalar shift left */ static void handle_scalar_simd_shli(DisasContext *s, bool insert, int immh, int immb, int opcode, @@ -9893,18 +9900,6 @@ static void disas_simd_scalar_shift_imm(DisasContext= *s, uint32_t insn) } =20 switch (opcode) { - case 0x08: /* SRI */ - if (!is_u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x00: /* SSHR / USHR */ - case 0x02: /* SSRA / USRA */ - case 0x04: /* SRSHR / URSHR */ - case 0x06: /* SRSRA / URSRA */ - handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); - break; case 0x0a: /* SHL / SLI */ handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); break; @@ -9940,6 +9935,11 @@ static void disas_simd_scalar_shift_imm(DisasContext= *s, uint32_t insn) handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn,= rd); break; default: + case 0x00: /* SSHR / USHR */ + case 0x02: /* SSRA / USRA */ + case 0x04: /* SRSHR / URSHR */ + case 0x06: /* SRSRA / URSRA */ + case 0x08: /* SRI */ unallocated_encoding(s); break; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 164ed575b9..6c2362b3bb 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -30,6 +30,7 @@ &rri_sf rd rn imm sf &i imm &rr_e rd rn esz +&rri_e rd rn imm esz &rrr_e rd rn rm esz &rrx_e rd rn rm idx esz &rrrr_e rd rn rm ra esz @@ -1285,3 +1286,18 @@ SHRN_v 0.00 11110 .... ... 10000 1 ..... ..= ... @q_shri_s RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_b RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_h RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_s + +# Advanced SIMD scalar shift by immediate + +@shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ + &rri_e esz=3D3 imm=3D%neon_rshift_i6 + +SSHR_s 0101 11110 .... ... 00000 1 ..... ..... @shri_d +USHR_s 0111 11110 .... ... 00000 1 ..... ..... @shri_d +SSRA_s 0101 11110 .... ... 00010 1 ..... ..... @shri_d +USRA_s 0111 11110 .... ... 00010 1 ..... ..... @shri_d +SRSHR_s 0101 11110 .... ... 00100 1 ..... ..... @shri_d +URSHR_s 0111 11110 .... ... 00100 1 ..... ..... @shri_d +SRSRA_s 0101 11110 .... ... 00110 1 ..... ..... @shri_d +URSRA_s 0111 11110 .... ... 00110 1 ..... ..... @shri_d +SRI_s 0111 11110 .... ... 01000 1 ..... ..... @shri_d --=20 2.43.0