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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108878; x=1726713678; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z6mFWajKHD8MStnRW2dfmIGlFFHAQdj7Jutp2KpIbAc=; b=w0f6o4a8Q+muV+Bxg0WMgAky5nPOuqhJONKmqNBoHRgp0DKrFIUOPop0hpTsQdW54E a7gww4euXy5+IA4DHKdkiRrs277SAS7Z1id4R97juQ4sEeHQS0LZX6rmszRSY1AYWL5a wFPpUcjIGfHjhtU6lYFnyO+bvzoR/rCo4dZwssRzl2JHz4gTU426/JhrDmzla4c8Hr6R TTTARn6LliUoLNp7aabc0RiYYsAT/mBd7KaJ8Ozc2UodwJWb6b7ZtwKHKTnBUtiLXFqW RuMbcNRHHMzu8pjes+J/cc2iywfVagIUP/rqbS+w46Wn8ethbcXHb1WxC1/YdNUHXDnF ZGsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108878; x=1726713678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z6mFWajKHD8MStnRW2dfmIGlFFHAQdj7Jutp2KpIbAc=; b=qic3lmbEdk371QHAA0P++ajjqzOi/VjwOfS73mxFTdWZvR1iLIuv1Suu+C6jiaUhqX WfQFyxW2j1DJG0rB4TMQu6ah6D7GrdryjmuQumLAkikR1B1K0Dlu/tEpv16QQUI106yM V/U8/CR8jU2Hx4eYSGXuEj78FCQr2enzjPllDVpft537BbZJcoCCGDvqBIsBwZQv/krx G5FT9LZQrPV6S06GcQiVfLS1IS/K9fefjQL95orwiC9n10XBheQMZNSgtDgSoVeWamnc McrFLsu38idgweBwx+J/uLqOlxYEeTl7TzafXIaGjHPe2zJjVNs9T2BlU0xwyHyxoU4b KHZA== X-Gm-Message-State: AOJu0Yyyc6slJak0qBGhO6N2Jyi8n2uSBTD8tAHBfdv9vCPrpNHmCKCR MJqfd7LpkEske+vZ1j3va5Agz18kQqRbR4sj+8tlUn5oUp9KaPSwCv86EJifcboGBN4uncl2WX3 c X-Google-Smtp-Source: AGHT+IGjldhzGyyT9on5Zy2hIgwDAnDXH+oBfrH/e9P3JqkPyZqog6SDXeGxlr9T4rqaUA/zcYx8yg== X-Received: by 2002:a17:903:98b:b0:206:9f91:3624 with SMTP id d9443c01a7336-2076e32fe49mr21047405ad.13.1726108877386; Wed, 11 Sep 2024 19:41:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 01/29] target/arm: Replace tcg_gen_dupi_vec with constants in gengvec.c Date: Wed, 11 Sep 2024 19:40:46 -0700 Message-ID: <20240912024114.1097832-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109077303116600 Content-Type: text/plain; charset="utf-8" Instead of copying a constant into a temporary with dupi, use a vector constant directly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 43 ++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 56a1dc1f75..726a1383ae 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -297,10 +297,9 @@ void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t s= h) static void gen_srshr_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t s= h) { TCGv_vec t =3D tcg_temp_new_vec_matching(d); - TCGv_vec ones =3D tcg_temp_new_vec_matching(d); + TCGv_vec ones =3D tcg_constant_vec_matching(d, vece, 1); =20 tcg_gen_shri_vec(vece, t, a, sh - 1); - tcg_gen_dupi_vec(vece, ones, 1); tcg_gen_and_vec(vece, t, t, ones); tcg_gen_sari_vec(vece, d, a, sh); tcg_gen_add_vec(vece, d, d, t); @@ -492,10 +491,9 @@ void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t s= h) static void gen_urshr_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t s= hift) { TCGv_vec t =3D tcg_temp_new_vec_matching(d); - TCGv_vec ones =3D tcg_temp_new_vec_matching(d); + TCGv_vec ones =3D tcg_constant_vec_matching(d, vece, 1); =20 tcg_gen_shri_vec(vece, t, a, shift - 1); - tcg_gen_dupi_vec(vece, ones, 1); tcg_gen_and_vec(vece, t, t, ones); tcg_gen_shri_vec(vece, d, a, shift); tcg_gen_add_vec(vece, d, d, t); @@ -685,9 +683,9 @@ static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t shift) static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t= sh) { TCGv_vec t =3D tcg_temp_new_vec_matching(d); - TCGv_vec m =3D tcg_temp_new_vec_matching(d); + int64_t mi =3D MAKE_64BIT_MASK((8 << vece) - sh, sh); + TCGv_vec m =3D tcg_constant_vec_matching(d, vece, mi); =20 - tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK((8 << vece) - sh, sh)); tcg_gen_shri_vec(vece, t, a, sh); tcg_gen_and_vec(vece, d, d, m); tcg_gen_or_vec(vece, d, d, t); @@ -773,10 +771,9 @@ static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, = int64_t shift) static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t= sh) { TCGv_vec t =3D tcg_temp_new_vec_matching(d); - TCGv_vec m =3D tcg_temp_new_vec_matching(d); + TCGv_vec m =3D tcg_constant_vec_matching(d, vece, MAKE_64BIT_MASK(0, s= h)); =20 tcg_gen_shli_vec(vece, t, a, sh); - tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK(0, sh)); tcg_gen_and_vec(vece, d, d, m); tcg_gen_or_vec(vece, d, d, t); } @@ -1044,14 +1041,13 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec ds= t, TCGv_vec rval =3D tcg_temp_new_vec_matching(dst); TCGv_vec lsh =3D tcg_temp_new_vec_matching(dst); TCGv_vec rsh =3D tcg_temp_new_vec_matching(dst); - TCGv_vec msk, max; + TCGv_vec max; =20 tcg_gen_neg_vec(vece, rsh, shift); if (vece =3D=3D MO_8) { tcg_gen_mov_vec(lsh, shift); } else { - msk =3D tcg_temp_new_vec_matching(dst); - tcg_gen_dupi_vec(vece, msk, 0xff); + TCGv_vec msk =3D tcg_constant_vec_matching(dst, vece, 0xff); tcg_gen_and_vec(vece, lsh, shift, msk); tcg_gen_and_vec(vece, rsh, rsh, msk); } @@ -1064,9 +1060,6 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec dst, tcg_gen_shlv_vec(vece, lval, src, lsh); tcg_gen_shrv_vec(vece, rval, src, rsh); =20 - max =3D tcg_temp_new_vec_matching(dst); - tcg_gen_dupi_vec(vece, max, 8 << vece); - /* * The choice of LT (signed) and GEU (unsigned) are biased toward * the instructions of the x86_64 host. For MO_8, the whole byte @@ -1074,6 +1067,7 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec dst, * have already masked to a byte and so a signed compare works. * Other tcg hosts have a full set of comparisons and do not care. */ + max =3D tcg_constant_vec_matching(dst, vece, 8 << vece); if (vece =3D=3D MO_8) { tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max); tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max); @@ -1170,6 +1164,7 @@ static void gen_sshl_vec(unsigned vece, TCGv_vec dst, TCGv_vec lsh =3D tcg_temp_new_vec_matching(dst); TCGv_vec rsh =3D tcg_temp_new_vec_matching(dst); TCGv_vec tmp =3D tcg_temp_new_vec_matching(dst); + TCGv_vec max, zero; =20 /* * Rely on the TCG guarantee that out of range shifts produce @@ -1180,15 +1175,15 @@ static void gen_sshl_vec(unsigned vece, TCGv_vec ds= t, if (vece =3D=3D MO_8) { tcg_gen_mov_vec(lsh, shift); } else { - tcg_gen_dupi_vec(vece, tmp, 0xff); - tcg_gen_and_vec(vece, lsh, shift, tmp); - tcg_gen_and_vec(vece, rsh, rsh, tmp); + TCGv_vec msk =3D tcg_constant_vec_matching(dst, vece, 0xff); + tcg_gen_and_vec(vece, lsh, shift, msk); + tcg_gen_and_vec(vece, rsh, rsh, msk); } =20 /* Bound rsh so out of bound right shift gets -1. */ - tcg_gen_dupi_vec(vece, tmp, (8 << vece) - 1); - tcg_gen_umin_vec(vece, rsh, rsh, tmp); - tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, tmp); + max =3D tcg_constant_vec_matching(dst, vece, (8 << vece) - 1); + tcg_gen_umin_vec(vece, rsh, rsh, max); + tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, max); =20 tcg_gen_shlv_vec(vece, lval, src, lsh); tcg_gen_sarv_vec(vece, rval, src, rsh); @@ -1197,12 +1192,12 @@ static void gen_sshl_vec(unsigned vece, TCGv_vec ds= t, tcg_gen_andc_vec(vece, lval, lval, tmp); =20 /* Select between left and right shift. */ + zero =3D tcg_constant_vec_matching(dst, vece, 0); if (vece =3D=3D MO_8) { - tcg_gen_dupi_vec(vece, tmp, 0); - tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, rval, lval); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, zero, rval, lval); } else { - tcg_gen_dupi_vec(vece, tmp, 0x80); - tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, lval, rval); + TCGv_vec sgn =3D tcg_constant_vec_matching(dst, vece, 0x80); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, sgn, lval, rval); } } =20 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109075; cv=none; d=zohomail.com; s=zohoarc; b=lhCnx3T4QAoUhW+fd9Qw7M31wZDcBg1GXwvXd+2sv+YUR8vNxBho615DAXp/NmdK1YLWjMhbSvdjyPJtL4ovcnQ+s6XVGZrmmuVrghmEyhAOySldmSWA7QDSwrqBiBaTVSSippCPhBEkJHsY+jaV+BthpGDhfIBlPqGz104qR88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109075; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZsgoXBUqhY92I8o0jSWWzMlp4jXjECIud5nMmIrPt6I=; b=MWnChxBMgtRfWfhAAVHQZQNgZsPPMK/6KTdocU4j2MVe/qhWkHoRs3T9kSzfggJQMY3Qe+DcOG5DBgmAssZjuEYP/sh906+SGeAx2T/idZJ+2aSptCYwwO2vzFQmJLm2KAsjA+bDitu2GQolXDW8EnO2kH0qx9EhGi+lIqWhnhY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172610907545443.428416359723315; Wed, 11 Sep 2024 19:44:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZlw-0002kH-9e; Wed, 11 Sep 2024 22:41:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlq-0002OT-Pc for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:22 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZln-00047Y-Tv for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:22 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-205659dc63aso5781535ad.1 for ; Wed, 11 Sep 2024 19:41:19 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108879; x=1726713679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZsgoXBUqhY92I8o0jSWWzMlp4jXjECIud5nMmIrPt6I=; b=zj0zM2wouUbn5tEzjBHcweljzO0zai7gHPOh7WKaN3x3Bqf2ERWF4QZf1BJScvhrAh TGS4PapknbY+c6AF0q5DXDbFB61lbDB6xxqGG+vfK78Kh1HpjfsKG5nvEpG1vt8hnwSd Lw+ssETk6MGWYaTC7tGZ6PJZdbbMDnmdCGCYovYlooMke3/fzWhSGqJF6vV/t10l4KVE RIsSMX6YK6tLmIQ/oEM4MORFJvl/9vNxqoTUz9878Lf774/n4O8E7j9hyM/ilqGvipTo SI+ndr0DE3OSBiHpi0JbjaKIa6t5VRhVtNsPqe/29vpE+Ueu4Mwmcz181tDzstj/H9TD wJCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108879; x=1726713679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZsgoXBUqhY92I8o0jSWWzMlp4jXjECIud5nMmIrPt6I=; b=D1Oq/WOfcUfCRAJLuz/EHLBoySOT8CuHvzW4Tv6kbJ21wxTUDjrxjbeVKy5NLJym/9 xtr8fKx4YUvyk+9zuggtWD0TH5W79PKi9Ues81ciwe01HMPZsnTn/kytSy0tdSGz2QVe 9zcyCCOSgleTA3xCQmtpXZ+O9qWmo374Q9wIJjZw8g4JQmT4EzSmp4ZtddqpOT9oqdkd d3d5oQd4/hb323p82wRrQ3vi+q4Zc84Jrv+bsZHmaiBpm5oNDMo0pCZXysQMH4k1NwQ+ /Pl1VFBg7ELuFMm3X2THtuavbCUoxZmnUFwFE7WBIpFrY8f91wm/wqJy+ef+PdYVEHgf jGRw== X-Gm-Message-State: AOJu0Yz2Bx1JYwqTDbuyV+Bj0/Rm2SI16sVTV1G6axHjoGtKgU2T6hfW Co/j20WemY+3Jv2jZq7PAGBmruXd/lKW8a+L1GIs8ZH8Epu+ElKQiHxjVcFHO1hjm/rU0WiL00C H X-Google-Smtp-Source: AGHT+IE0woZJtAydXjkhfSoDwSeoFG06JP4UWD4Yt3oaXJPkQ3ero7Al7c6RKuFPPr3o3Djja/vOzg== X-Received: by 2002:a17:903:1d2:b0:206:fea3:b9f6 with SMTP id d9443c01a7336-2076e3d580amr19157765ad.25.1726108878342; Wed, 11 Sep 2024 19:41:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 02/29] target/arm: Replace tcg_gen_dupi_vec with constants in translate-sve.c Date: Wed, 11 Sep 2024 19:40:47 -0700 Message-ID: <20240912024114.1097832-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109077155116600 Content-Type: text/plain; charset="utf-8" Instead of copying a constant into a temporary with dupi, use a vector constant directly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 128 +++++++++++++-------------------- 1 file changed, 49 insertions(+), 79 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 9e2536dfe9..49d32fabc9 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -6081,9 +6081,9 @@ static void gen_sshll_vec(unsigned vece, TCGv_vec d, = TCGv_vec n, int64_t imm) =20 if (top) { if (shl =3D=3D halfbits) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); - tcg_gen_and_vec(vece, d, n, t); + tcg_gen_and_vec(vece, d, n, + tcg_constant_vec_matching(d, vece, + MAKE_64BIT_MASK(halfbits, halfbits))); } else { tcg_gen_sari_vec(vece, d, n, halfbits); tcg_gen_shli_vec(vece, d, d, shl); @@ -6138,18 +6138,18 @@ static void gen_ushll_vec(unsigned vece, TCGv_vec d= , TCGv_vec n, int64_t imm) =20 if (top) { if (shl =3D=3D halfbits) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); - tcg_gen_and_vec(vece, d, n, t); + tcg_gen_and_vec(vece, d, n, + tcg_constant_vec_matching(d, vece, + MAKE_64BIT_MASK(halfbits, halfbits))); } else { tcg_gen_shri_vec(vece, d, n, halfbits); tcg_gen_shli_vec(vece, d, d, shl); } } else { if (shl =3D=3D 0) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_and_vec(vece, d, n, t); + tcg_gen_and_vec(vece, d, n, + tcg_constant_vec_matching(d, vece, + MAKE_64BIT_MASK(0, halfbits))); } else { tcg_gen_shli_vec(vece, d, n, halfbits); tcg_gen_shri_vec(vece, d, d, halfbits - shl); @@ -6317,18 +6317,14 @@ static const TCGOpcode sqxtn_list[] =3D { =20 static void gen_sqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t mask =3D (1ull << halfbits) - 1; int64_t min =3D -1ull << (halfbits - 1); int64_t max =3D -min - 1; =20 - tcg_gen_dupi_vec(vece, t, min); - tcg_gen_smax_vec(vece, d, n, t); - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_smin_vec(vece, d, d, t); - tcg_gen_dupi_vec(vece, t, mask); - tcg_gen_and_vec(vece, d, d, t); + tcg_gen_smax_vec(vece, d, n, tcg_constant_vec_matching(d, vece, min)); + tcg_gen_smin_vec(vece, d, d, tcg_constant_vec_matching(d, vece, max)); + tcg_gen_and_vec(vece, d, d, tcg_constant_vec_matching(d, vece, mask)); } =20 static const GVecGen2 sqxtnb_ops[3] =3D { @@ -6349,19 +6345,15 @@ TRANS_FEAT(SQXTNB, aa64_sve2, do_narrow_extract, a,= sqxtnb_ops) =20 static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t mask =3D (1ull << halfbits) - 1; int64_t min =3D -1ull << (halfbits - 1); int64_t max =3D -min - 1; =20 - tcg_gen_dupi_vec(vece, t, min); - tcg_gen_smax_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_smin_vec(vece, n, n, t); + tcg_gen_smax_vec(vece, n, n, tcg_constant_vec_matching(d, vece, min)); + tcg_gen_smin_vec(vece, n, n, tcg_constant_vec_matching(d, vece, max)); tcg_gen_shli_vec(vece, n, n, halfbits); - tcg_gen_dupi_vec(vece, t, mask); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, tcg_constant_vec_matching(d, vece, mask), = d, n); } =20 static const GVecGen2 sqxtnt_ops[3] =3D { @@ -6389,12 +6381,10 @@ static const TCGOpcode uqxtn_list[] =3D { =20 static void gen_uqxtnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t max =3D (1ull << halfbits) - 1; =20 - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_umin_vec(vece, d, n, t); + tcg_gen_umin_vec(vece, d, n, tcg_constant_vec_matching(d, vece, max)); } =20 static const GVecGen2 uqxtnb_ops[3] =3D { @@ -6415,14 +6405,13 @@ TRANS_FEAT(UQXTNB, aa64_sve2, do_narrow_extract, a,= uqxtnb_ops) =20 static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t max =3D (1ull << halfbits) - 1; + TCGv_vec maxv =3D tcg_constant_vec_matching(d, vece, max); =20 - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_umin_vec(vece, n, n, t); + tcg_gen_umin_vec(vece, n, n, maxv); tcg_gen_shli_vec(vece, n, n, halfbits); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, maxv, d, n); } =20 static const GVecGen2 uqxtnt_ops[3] =3D { @@ -6450,14 +6439,11 @@ static const TCGOpcode sqxtun_list[] =3D { =20 static void gen_sqxtunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t max =3D (1ull << halfbits) - 1; =20 - tcg_gen_dupi_vec(vece, t, 0); - tcg_gen_smax_vec(vece, d, n, t); - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_umin_vec(vece, d, d, t); + tcg_gen_smax_vec(vece, d, n, tcg_constant_vec_matching(d, vece, 0)); + tcg_gen_umin_vec(vece, d, d, tcg_constant_vec_matching(d, vece, max)); } =20 static const GVecGen2 sqxtunb_ops[3] =3D { @@ -6478,16 +6464,14 @@ TRANS_FEAT(SQXTUNB, aa64_sve2, do_narrow_extract, a= , sqxtunb_ops) =20 static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t max =3D (1ull << halfbits) - 1; + TCGv_vec maxv =3D tcg_constant_vec_matching(d, vece, max); =20 - tcg_gen_dupi_vec(vece, t, 0); - tcg_gen_smax_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_umin_vec(vece, n, n, t); + tcg_gen_smax_vec(vece, n, n, tcg_constant_vec_matching(d, vece, 0)); + tcg_gen_umin_vec(vece, n, n, maxv); tcg_gen_shli_vec(vece, n, n, halfbits); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, maxv, d, n); } =20 static const GVecGen2 sqxtunt_ops[3] =3D { @@ -6551,13 +6535,11 @@ static void gen_shrnb64_i64(TCGv_i64 d, TCGv_i64 n,= int64_t shr) =20 static void gen_shrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t s= hr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; uint64_t mask =3D MAKE_64BIT_MASK(0, halfbits); =20 tcg_gen_shri_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, mask); - tcg_gen_and_vec(vece, d, n, t); + tcg_gen_and_vec(vece, d, n, tcg_constant_vec_matching(d, vece, mask)); } =20 static const TCGOpcode shrnb_vec_list[] =3D { INDEX_op_shri_vec, 0 }; @@ -6609,13 +6591,11 @@ static void gen_shrnt64_i64(TCGv_i64 d, TCGv_i64 n,= int64_t shr) =20 static void gen_shrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t s= hr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; uint64_t mask =3D MAKE_64BIT_MASK(0, halfbits); =20 tcg_gen_shli_vec(vece, n, n, halfbits - shr); - tcg_gen_dupi_vec(vece, t, mask); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, tcg_constant_vec_matching(d, vece, mask), = d, n); } =20 static const TCGOpcode shrnt_vec_list[] =3D { INDEX_op_shli_vec, 0 }; @@ -6658,14 +6638,12 @@ TRANS_FEAT(RSHRNT, aa64_sve2, do_shr_narrow, a, rsh= rnt_ops) static void gen_sqshrunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; + uint64_t max =3D MAKE_64BIT_MASK(0, halfbits); =20 tcg_gen_sari_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, 0); - tcg_gen_smax_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_umin_vec(vece, d, n, t); + tcg_gen_smax_vec(vece, n, n, tcg_constant_vec_matching(d, vece, 0)); + tcg_gen_umin_vec(vece, d, n, tcg_constant_vec_matching(d, vece, max)); } =20 static const TCGOpcode sqshrunb_vec_list[] =3D { @@ -6690,16 +6668,15 @@ TRANS_FEAT(SQSHRUNB, aa64_sve2, do_shr_narrow, a, s= qshrunb_ops) static void gen_sqshrunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; + uint64_t max =3D MAKE_64BIT_MASK(0, halfbits); + TCGv_vec maxv =3D tcg_constant_vec_matching(d, vece, max); =20 tcg_gen_sari_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, 0); - tcg_gen_smax_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_umin_vec(vece, n, n, t); + tcg_gen_smax_vec(vece, n, n, tcg_constant_vec_matching(d, vece, 0)); + tcg_gen_umin_vec(vece, n, n, maxv); tcg_gen_shli_vec(vece, n, n, halfbits); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, maxv, d, n); } =20 static const TCGOpcode sqshrunt_vec_list[] =3D { @@ -6742,18 +6719,15 @@ TRANS_FEAT(SQRSHRUNT, aa64_sve2, do_shr_narrow, a, = sqrshrunt_ops) static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t max =3D MAKE_64BIT_MASK(0, halfbits - 1); int64_t min =3D -max - 1; + int64_t mask =3D MAKE_64BIT_MASK(0, halfbits); =20 tcg_gen_sari_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, min); - tcg_gen_smax_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_smin_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_and_vec(vece, d, n, t); + tcg_gen_smax_vec(vece, n, n, tcg_constant_vec_matching(d, vece, min)); + tcg_gen_smin_vec(vece, n, n, tcg_constant_vec_matching(d, vece, max)); + tcg_gen_and_vec(vece, d, n, tcg_constant_vec_matching(d, vece, mask)); } =20 static const TCGOpcode sqshrnb_vec_list[] =3D { @@ -6778,19 +6752,16 @@ TRANS_FEAT(SQSHRNB, aa64_sve2, do_shr_narrow, a, sq= shrnb_ops) static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; int64_t max =3D MAKE_64BIT_MASK(0, halfbits - 1); int64_t min =3D -max - 1; + int64_t mask =3D MAKE_64BIT_MASK(0, halfbits); =20 tcg_gen_sari_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, min); - tcg_gen_smax_vec(vece, n, n, t); - tcg_gen_dupi_vec(vece, t, max); - tcg_gen_smin_vec(vece, n, n, t); + tcg_gen_smax_vec(vece, n, n, tcg_constant_vec_matching(d, vece, min)); + tcg_gen_smin_vec(vece, n, n, tcg_constant_vec_matching(d, vece, max)); tcg_gen_shli_vec(vece, n, n, halfbits); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, tcg_constant_vec_matching(d, vece, mask), = d, n); } =20 static const TCGOpcode sqshrnt_vec_list[] =3D { @@ -6833,12 +6804,11 @@ TRANS_FEAT(SQRSHRNT, aa64_sve2, do_shr_narrow, a, s= qrshrnt_ops) static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; + int64_t max =3D MAKE_64BIT_MASK(0, halfbits); =20 tcg_gen_shri_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_umin_vec(vece, d, n, t); + tcg_gen_umin_vec(vece, d, n, tcg_constant_vec_matching(d, vece, max)); } =20 static const TCGOpcode uqshrnb_vec_list[] =3D { @@ -6863,14 +6833,14 @@ TRANS_FEAT(UQSHRNB, aa64_sve2, do_shr_narrow, a, uq= shrnb_ops) static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) { - TCGv_vec t =3D tcg_temp_new_vec_matching(d); int halfbits =3D 4 << vece; + int64_t max =3D MAKE_64BIT_MASK(0, halfbits); + TCGv_vec maxv =3D tcg_constant_vec_matching(d, vece, max); =20 tcg_gen_shri_vec(vece, n, n, shr); - tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); - tcg_gen_umin_vec(vece, n, n, t); + tcg_gen_umin_vec(vece, n, n, maxv); tcg_gen_shli_vec(vece, n, n, halfbits); - tcg_gen_bitsel_vec(vece, d, t, d, n); + tcg_gen_bitsel_vec(vece, d, maxv, d, n); } =20 static const TCGOpcode uqshrnt_vec_list[] =3D { --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108879; x=1726713679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9bC2pdgCZhVH53QkJRlqyhl6QihYCpdmu7xOBS4i9k0=; b=cq+f0a82nCQzp2+BORa1OUtfwFFj/zFsu1Rg9UNt1kZkyhCC2FEWxxHIjpCf761xPB 0hA2+4vZ/sRKTLwFhPEYjUWAiU4BzcKDtnamZ6BMOTJltKOhal/zZla5fpJ/zGt/R3l7 GjFkaQziJqx3iVsBNiCT6fN2azYi0BnSFtGKMKJXJOJhbs4iekMiFhAmx3GbCQpLSDre yT+7jgKWW2XUPbN6NfNiDaBZMfjpS34Ka4JQ3RmZEOV84Xfd0nqkI2nRcNNIOemteoVo msCckXNRBX/Hprc007hyKGrCAj6cxnBoUCjSAKszBaYlaU06DnXyjFZEN+FHllHYu0qn 5t5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108879; x=1726713679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9bC2pdgCZhVH53QkJRlqyhl6QihYCpdmu7xOBS4i9k0=; b=IBeSwdXgXsxVoelUPiugqR8Xj7lhMDVgHispsh8BtzuIDEULENMYvuyEE4YgqoodKC RbG3XFMsTrrFBvGoqcRtVetSDl9WDZ5iO1D3KdMhZfJGH52ezR2eBAZZn2ty64lFbUNt CJexL1bEMHr1R4rcnJU+jHMSd9xOzuWee+0GCgfWeeifOKocTdHccFos4sSdhCp58B5v vYYZKiy1g7CefvVeaM6RLgSdXMvPg487c680A6u66/dDjHQ7fZitWfT8q7LjpAr0ierQ rEbJ2SZZ96/gA/zvlHubCy8d0t2rvogY37CEWjlvNsKekrOo6jf9bDjsG7eQJslo0/3r tuLA== X-Gm-Message-State: AOJu0YxvlHu0otWIR1nuxGQQLQ5UC8EQ0bUueOHWvVzmbc5+IUPBEHHQ dwlGT9FzRj0T8qTAgdqxXTU8BgNtmcaPl+CVsMPciJ3fUGvMkLvC2FgnjGg2xu7o6KZWBP1LiFX Z X-Google-Smtp-Source: AGHT+IHBC3qMCoGyvsKYyAFCOBf83Esal77HSba8NJ5nlRcffgKDCpZJIdm7Z42m5+YfFKULuxVd6Q== X-Received: by 2002:a17:903:190:b0:206:cbf0:3089 with SMTP id d9443c01a7336-2076e44e010mr17777605ad.54.1726108879377; Wed, 11 Sep 2024 19:41:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 03/29] target/arm: Use cmpsel in gen_ushl_vec Date: Wed, 11 Sep 2024 19:40:48 -0700 Message-ID: <20240912024114.1097832-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108908956116600 Content-Type: text/plain; charset="utf-8" Instead of cmp+and or cmp+andc, use cmpsel. This will be better for hosts that use predicate registers for cmp. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 726a1383ae..3edbf3a262 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -1041,7 +1041,7 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec dst, TCGv_vec rval =3D tcg_temp_new_vec_matching(dst); TCGv_vec lsh =3D tcg_temp_new_vec_matching(dst); TCGv_vec rsh =3D tcg_temp_new_vec_matching(dst); - TCGv_vec max; + TCGv_vec max, zero; =20 tcg_gen_neg_vec(vece, rsh, shift); if (vece =3D=3D MO_8) { @@ -1061,23 +1061,20 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec ds= t, tcg_gen_shrv_vec(vece, rval, src, rsh); =20 /* - * The choice of LT (signed) and GEU (unsigned) are biased toward + * The choice of GE (signed) and GEU (unsigned) are biased toward * the instructions of the x86_64 host. For MO_8, the whole byte * is significant so we must use an unsigned compare; otherwise we * have already masked to a byte and so a signed compare works. * Other tcg hosts have a full set of comparisons and do not care. */ + zero =3D tcg_constant_vec_matching(dst, vece, 0); max =3D tcg_constant_vec_matching(dst, vece, 8 << vece); if (vece =3D=3D MO_8) { - tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max); - tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max); - tcg_gen_andc_vec(vece, lval, lval, lsh); - tcg_gen_andc_vec(vece, rval, rval, rsh); + tcg_gen_cmpsel_vec(TCG_COND_GEU, vece, lval, lsh, max, zero, lval); + tcg_gen_cmpsel_vec(TCG_COND_GEU, vece, rval, rsh, max, zero, rval); } else { - tcg_gen_cmp_vec(TCG_COND_LT, vece, lsh, lsh, max); - tcg_gen_cmp_vec(TCG_COND_LT, vece, rsh, rsh, max); - tcg_gen_and_vec(vece, lval, lval, lsh); - tcg_gen_and_vec(vece, rval, rval, rsh); + tcg_gen_cmpsel_vec(TCG_COND_GE, vece, lval, lsh, max, zero, lval); + tcg_gen_cmpsel_vec(TCG_COND_GE, vece, rval, rsh, max, zero, rval); } tcg_gen_or_vec(vece, dst, lval, rval); } @@ -1087,7 +1084,7 @@ void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { static const TCGOpcode vecop_list[] =3D { INDEX_op_neg_vec, INDEX_op_shlv_vec, - INDEX_op_shrv_vec, INDEX_op_cmp_vec, 0 + INDEX_op_shrv_vec, INDEX_op_cmpsel_vec, 0 }; static const GVecGen3 ops[4] =3D { { .fniv =3D gen_ushl_vec, --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109129; cv=none; d=zohomail.com; s=zohoarc; b=d/sKs+EB525o3KFKD4BuOj3fq050KX1aHOUk2jSyamSxCaTIY5g18nf0QprqyWTPLYN+9nIk62lXdIleDjx/eW9sATq3KDteVXf8+7k2HnMpQ6YHctwGRe5anErIZy6E43oxiLgh5B3kLp2XQvEMNfTVxMmNag+uS1tqZhVRFQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109129; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=d3AYwzPdHoHu5Aos81gdCbKTZ5PvIr4Bh9qOHvqoApc=; b=FD4DLxtWXHwtPTB24/ej9i5ndxklKHRwi6nD65DUvgkzYp6aq86othD5wJ71uRMNo+AX1Dx1+iCvluET12+bKX3hQ0pf1bOmqUdC/OnrHkGoIv3s0F+xYJuGg+m8UBoF/Xf1g76puj2uZpfXGzJG1qF8uypZWBkD3eNP+maCg7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109129486563.1640980312593; Wed, 11 Sep 2024 19:45:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm0-00033P-LW; Wed, 11 Sep 2024 22:41:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlr-0002TR-R1 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:24 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlp-000483-RK for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:23 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-205909afad3so5585285ad.2 for ; Wed, 11 Sep 2024 19:41:21 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108880; x=1726713680; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d3AYwzPdHoHu5Aos81gdCbKTZ5PvIr4Bh9qOHvqoApc=; b=Rd8TeEjWqzwKADlbshioFVUe2NjnKi/9TItdr67iKodPhsAHjAwGR+aRBVBRZelHiA CiGcrDLp3g33nbX/Lptd2mp9UWRDl6u/Tzr3UR/WndO9hwYSQ5w1xrjQ52kDUVU8JtlW 2byd6XmF++NJZ0FrYBiRdF0VIKyF7xIrQwhg0FZbi0XkDr4uAaD5kM+BJdL7FV/+EfnV U3+8As4aN4SRY+S8Rm+jMOp+Cm0YcdrwER0lzGPqhIR5oTqL9KHy7fLSokkdYURL+nqT XPm1iHitZidbzIvRGhqNwMIceySQ1cTA/Hg7rzyyEVBmpQMdkTYSeV2wFsbuPWxyqiyV yxxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108880; x=1726713680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d3AYwzPdHoHu5Aos81gdCbKTZ5PvIr4Bh9qOHvqoApc=; b=CtLptHNkxr2kq+ovn6vhvtQR5uIZG9FiE2gyaRKCFJ2TKoCWXoH2P3HR4POvc79NUV uDQr7zfrWgWeXX3D4NkkiACN9LBUHiyOk5IWZS11RPOvCHSO1Cd72XQL1uEt+6oS5ulT Al2KT1GSNVgMcb5r7j9+H1lAcZjRJZAuZRDS/lNWvFYezHs4kx79pf1wn9/e1fMHbO33 hwS7D/dRZOMJCmyZ0ShFcDChgZnCi0AkSvAUX5IL6WBQIZZLjtgWLYA5W4Wwgi2edcGJ tBil0yflDaT8AqljFtTiKjkKz9NkiGVt/y/i6jxb4wnupua49myW2SE7eRP0jzNCqsYd w9Lg== X-Gm-Message-State: AOJu0Ywg/p6IqHvPItDQyRpI5xo5qVW/WkCE6DrZNf9emGsMShn41TOC JHl9RheZ9Ym2y1mZb0UDL1trRFEMCzTXZag+rr+LA7F2NUfRwC8elZ4/v1YiKI5gLcRCCKa9MAg c X-Google-Smtp-Source: AGHT+IGpAslnmdfyBv4B2dXg7q51gDKgk891akWC7lkjFjMeRfKCA6yLmdGBOCQGgMPZr8O+8fM+gA== X-Received: by 2002:a17:903:1c6:b0:207:7537:c651 with SMTP id d9443c01a7336-2077537c765mr9232715ad.45.1726108880473; Wed, 11 Sep 2024 19:41:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 04/29] target/arm: Use cmpsel in gen_sshl_vec Date: Wed, 11 Sep 2024 19:40:49 -0700 Message-ID: <20240912024114.1097832-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109131383116600 Content-Type: text/plain; charset="utf-8" Instead of cmp+and or cmp+andc, use cmpsel. This will be better for hosts that use predicate registers for cmp. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 3edbf3a262..c5fc1b6cfb 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -1160,7 +1160,6 @@ static void gen_sshl_vec(unsigned vece, TCGv_vec dst, TCGv_vec rval =3D tcg_temp_new_vec_matching(dst); TCGv_vec lsh =3D tcg_temp_new_vec_matching(dst); TCGv_vec rsh =3D tcg_temp_new_vec_matching(dst); - TCGv_vec tmp =3D tcg_temp_new_vec_matching(dst); TCGv_vec max, zero; =20 /* @@ -1180,16 +1179,15 @@ static void gen_sshl_vec(unsigned vece, TCGv_vec ds= t, /* Bound rsh so out of bound right shift gets -1. */ max =3D tcg_constant_vec_matching(dst, vece, (8 << vece) - 1); tcg_gen_umin_vec(vece, rsh, rsh, max); - tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, max); =20 tcg_gen_shlv_vec(vece, lval, src, lsh); tcg_gen_sarv_vec(vece, rval, src, rsh); =20 /* Select in-bound left shift. */ - tcg_gen_andc_vec(vece, lval, lval, tmp); + zero =3D tcg_constant_vec_matching(dst, vece, 0); + tcg_gen_cmpsel_vec(TCG_COND_GT, vece, lval, lsh, max, zero, lval); =20 /* Select between left and right shift. */ - zero =3D tcg_constant_vec_matching(dst, vece, 0); if (vece =3D=3D MO_8) { tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, zero, rval, lval); } else { @@ -1203,7 +1201,7 @@ void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, ui= nt32_t rn_ofs, { static const TCGOpcode vecop_list[] =3D { INDEX_op_neg_vec, INDEX_op_umin_vec, INDEX_op_shlv_vec, - INDEX_op_sarv_vec, INDEX_op_cmp_vec, INDEX_op_cmpsel_vec, 0 + INDEX_op_sarv_vec, INDEX_op_cmpsel_vec, 0 }; static const GVecGen3 ops[4] =3D { { .fniv =3D gen_sshl_vec, --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109185; cv=none; d=zohomail.com; s=zohoarc; b=YSsHJHTqPrXa8EkUJb66gCsOGRCPHztF63KAp0V/Xpoj+f5ygqNe+CcPuOeoOtYaVulzPB5EC9XuKnOQbs9v3H/FFgePEEothQO4nyRBCSvhpYAtC/dZwFPBxqkp5eIRCxa33FO/3y6LFPFueT8//IpWKp2n6DSI2hp+1MLuruQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109185; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hCg9x0mWGGumEFO2TzIOUcSJLT2z1d9b8LgujqgHrcQ=; b=DKZoNHkhXCA0irtx5//K743b5NH+MQ40AAkAKT3O2cWX/TvAfo6riBdPxE1H1wrbQGf4jMBa5cXjTLBUqb9Sf8WilLfOfw17iIBVbZOvEblhpxAcxNfiYtwCkVhUx7xNjI8Ms41i82rgk8RVGmLWC7oFN+37fQiUYAvD8O3SW90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109185203222.60788273845492; Wed, 11 Sep 2024 19:46:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm0-00032p-G3; Wed, 11 Sep 2024 22:41:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZls-0002Y8-Vt for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:25 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlq-00048G-Vv for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:24 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-205909af9b5so4843015ad.3 for ; Wed, 11 Sep 2024 19:41:22 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108881; x=1726713681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hCg9x0mWGGumEFO2TzIOUcSJLT2z1d9b8LgujqgHrcQ=; b=M96BesC8+ranaxrZVRoK0ii5RnS7u+2YOJ+twAhaPXPh4Sx07x3CyfX/yupHI1rSZT 11tFi4/xhpms1gqS/wweCA58rzEUkUgexdSRI29tk9h9pNwjHYUwvDkuOpWAqlyhpYHp ScoyjZST5O9fj4pSJ5xS9npDKfWu6bCKDO3vr7rB7tL6p+2iB96bu3yGkgCvsF0Jn7bW IyN6BlstV70Phr90MC1a/d6Gm4bcaYKOTE9eoPJWLxTwAliud/N6ZV1vgaOFiuVTNUMq QZ/6DUXiEPykLJgygYDnkm9V9fPXXTsBWgFAu9/PFTlhsZL/8B4n9Fi11DVsM+B/ScbI tG0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108881; x=1726713681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hCg9x0mWGGumEFO2TzIOUcSJLT2z1d9b8LgujqgHrcQ=; b=agyXJUwDrhNuAsyViKajFbg1oh4bjds+xz7bC3ll0MH5Qqe34oMiW5hM2rayDsZmII aJoAaDwXGrxWFA5vLlfMzT1paM2LFfTsOHqJ8AKduZRiDb38kkfWJAp3DDVvQRNbg7Kh KsGVbIGVRlb0ftugi7sg+8JpUGD+szv9PmGNlPTSHxif4Qx5s1SOqlHkz+ndpjZDBQyN GR0syhigbJvxyvH4nq1wwuKzHivEN2/vaLuqaNVeZKMe+DQDy1nA99/LA23HlX/jid2I cn6guti8WDDtDkBlyfPDyw5uMRF4YToX3miwOcQhPfN7Pnrm9GfZHwOourhtpWEML9m5 n4HQ== X-Gm-Message-State: AOJu0YwPVx+UuKWgox2pEbM4fwpw2qbSpJyK1+I1h52HSEjSqd8SVHxh QLlOpTz0B5H4I2DPES8rIeCKlfmLwALTXfSh0BbTK9ArtJ+dusX2QbEetXhdKKSxgUv1fyvb3B0 O X-Google-Smtp-Source: AGHT+IFEZmRj29/TzxoOD+1SbMd48hn4OPd3U+E2TCkhZzH4Y6MFgMVy7LNSGeZVqby0aFDPknXXdQ== X-Received: by 2002:a17:903:2302:b0:207:20c5:42c with SMTP id d9443c01a7336-2076e40be2dmr22874495ad.45.1726108881334; Wed, 11 Sep 2024 19:41:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 05/29] target/arm: Use tcg_gen_extract2_i64 for EXT Date: Wed, 11 Sep 2024 19:40:50 -0700 Message-ID: <20240912024114.1097832-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109185634116600 The extract2 tcg op performs the same operation as the do_ext64 function. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6d5f12e8f5..1a0b2bb33b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8890,23 +8890,6 @@ static void disas_data_proc_fp(DisasContext *s, uint= 32_t insn) } } =20 -static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_righ= t, - int pos) -{ - /* Extract 64 bits from the middle of two concatenated 64 bit - * vector register slices left:right. The extracted bits start - * at 'pos' bits into the right (least significant) side. - * We return the result in tcg_right, and guarantee not to - * trash tcg_left. - */ - TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); - assert(pos > 0 && pos < 64); - - tcg_gen_shri_i64(tcg_right, tcg_right, pos); - tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); - tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); -} - /* EXT * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 * +---+---+-------------+-----+---+------+---+------+---+------+------+ @@ -8944,7 +8927,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) read_vec_element(s, tcg_resl, rn, 0, MO_64); if (pos !=3D 0) { read_vec_element(s, tcg_resh, rm, 0, MO_64); - do_ext64(s, tcg_resh, tcg_resl, pos); + tcg_gen_extract2_i64(tcg_resl, tcg_resl, tcg_resh, pos); } } else { TCGv_i64 tcg_hh; @@ -8965,10 +8948,10 @@ static void disas_simd_ext(DisasContext *s, uint32_= t insn) read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); elt++; if (pos !=3D 0) { - do_ext64(s, tcg_resh, tcg_resl, pos); + tcg_gen_extract2_i64(tcg_resl, tcg_resl, tcg_resh, pos); tcg_hh =3D tcg_temp_new_i64(); read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); - do_ext64(s, tcg_hh, tcg_resh, pos); + tcg_gen_extract2_i64(tcg_resh, tcg_resh, tcg_hh, pos); } } =20 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726108984; cv=none; d=zohomail.com; s=zohoarc; b=N2fD3xE/xIzt7kWb8OBxIasq0/zN0lPN17STxx8r8D3pY5faxFHIlkqethXq8rQFB0RgE4wyzu01erKY4ckxAajNKVt10ZF6hDL3dd5VQyK2og66EKc2NQqgiIFV/TtH25A87PmhIbvmprO1QANLPT5jbEcdGACHdDef2kmrxSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726108984; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bjTWmYibNX9ocSHJzCOY3s0qFLQcqbQGzAuMMbaGtYs=; b=QEPVxrW7EvxzPiCnnccIjum8dpuFs83aL4HwO4G20y82KHgtLShInRA4ZJCiyINl10j7jUk/ULZXBsC5umufz0GjS3P8RztbvsrNnbcyycWJv3+7IarwOroDQQjfhwN+bJPKtR42OS+npuozgtRzCYFlZpY7G0h8JqfyQQ5EQz4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726108984232606.0023335761402; Wed, 11 Sep 2024 19:43:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm2-00039r-1n; Wed, 11 Sep 2024 22:41:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlt-0002ZM-A7 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:25 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlr-00048i-H8 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:25 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-201d5af11a4so5816825ad.3 for ; Wed, 11 Sep 2024 19:41:23 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108882; x=1726713682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bjTWmYibNX9ocSHJzCOY3s0qFLQcqbQGzAuMMbaGtYs=; b=yNjtlxVd2Sj0j+JG49DI4PFfJxhkQUg3nzHuIKac0YUwF6nwNJpDTz157Eoma5GRca OsjG+c/3nqzovfSlw05f9vx/xJrJeR6qZQe5XiniLGxaz5nQ1jsMNSgaO1a5sK5Ev1kU B9IKDLTWWCuevpa+dZS56BG5cMjl9xIJepKHrcgKPqa1xbSnWu/p1E8iV445lNS4B6CF 6GvK4Tp/SXbcYmJ5aBGABm5/09BtgmFIHxHJMBF0To0qgHb2SZAMfEBt95SbXWWNlXRh vKfeT/oXuAoDbn033A0i9KkB5qH3UYoNYZxF4SkbzwKjgVmkNqfc4XT62Bhy/LxA3GLj TL2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108882; x=1726713682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bjTWmYibNX9ocSHJzCOY3s0qFLQcqbQGzAuMMbaGtYs=; b=sVqEDD1NrPVp60eI7lopfJNYVPYEhNVeWKkJFfc8rrUJ3lJ0ER3c9sfpvRyucMkKG+ aGdAgVYF9eGP4jgfnRpoDyUXfkzPAnkWe2RlDIP9WwrAhbC1S62ruGLc99m1vH00ksVv tfXWauCTLYrF7lD5blLW3i+9Vw9+xV6OGAbe7WAJLairvjfX0vTyfWou+nT+U/ckrhdJ XechKvAl1G7SqGXA3RaZFHljD2FZ+PtNHoimSo1ilHUtzHcto1QaQsVTVfLG6assc0mP w6xqrDlP5rbIY38fy63YZpjnhdjgKXBQOYdNpl9LNmqIOH2fj2qbzlyt00+ueBy6rtDP 3aeA== X-Gm-Message-State: AOJu0Yx4qpTzdJcGrDyj2ANOhoXWYVGCzmtK4JzsUIMGChpaNMDtlN2O /WipizF9fwRkktZP7RL5EOxbhL/MAi258itvf7YAnUAbN7morBIqtDRnc+WTiSYuiiHwdCjjbwQ 2 X-Google-Smtp-Source: AGHT+IFfHuXgJEcxm9IaT85NJDNuL7JIf2e8+2XP9DJ3fDqSqlgx6NLQB64dZ3Eua+fKFUiMrLrMEw== X-Received: by 2002:a17:903:230e:b0:206:cfb3:7232 with SMTP id d9443c01a7336-2076e3f3ae4mr22978005ad.48.1726108882166; Wed, 11 Sep 2024 19:41:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 06/29] target/arm: Convert EXT to decodetree Date: Wed, 11 Sep 2024 19:40:51 -0700 Message-ID: <20240912024114.1097832-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108984787116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 121 +++++++++++++-------------------- target/arm/tcg/a64.decode | 5 ++ 2 files changed, 53 insertions(+), 73 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1a0b2bb33b..48188d4116 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6582,6 +6582,54 @@ static bool trans_FCSEL(DisasContext *s, arg_FCSEL *= a) return true; } =20 +/* + * Advanced SIMD Extract + */ + +static bool trans_EXT_d(DisasContext *s, arg_EXT_d *a) +{ + if (fp_access_check(s)) { + TCGv_i64 lo =3D read_fp_dreg(s, a->rn); + if (a->imm !=3D 0) { + TCGv_i64 hi =3D read_fp_dreg(s, a->rm); + tcg_gen_extract2_i64(lo, lo, hi, a->imm * 8); + } + write_fp_dreg(s, a->rd, lo); + } + return true; +} + +static bool trans_EXT_q(DisasContext *s, arg_EXT_q *a) +{ + TCGv_i64 lo, hi; + int pos =3D (a->imm & 7) * 8; + int elt =3D a->imm >> 3; + + if (!fp_access_check(s)) { + return true; + } + + lo =3D tcg_temp_new_i64(); + hi =3D tcg_temp_new_i64(); + + read_vec_element(s, lo, a->rn, elt, MO_64); + elt++; + read_vec_element(s, hi, elt & 2 ? a->rm : a->rn, elt & 1, MO_64); + elt++; + + if (pos !=3D 0) { + TCGv_i64 hh =3D tcg_temp_new_i64(); + tcg_gen_extract2_i64(lo, lo, hi, pos); + read_vec_element(s, hh, a->rm, elt & 1, MO_64); + tcg_gen_extract2_i64(hi, hi, hh, pos); + } + + write_vec_element(s, lo, a->rd, 0, MO_64); + write_vec_element(s, hi, a->rd, 1, MO_64); + clear_vec_high(s, true, a->rd); + return true; +} + /* * Floating-point data-processing (3 source) */ @@ -8890,78 +8938,6 @@ static void disas_data_proc_fp(DisasContext *s, uint= 32_t insn) } } =20 -/* EXT - * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 - * +---+---+-------------+-----+---+------+---+------+---+------+------+ - * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | - * +---+---+-------------+-----+---+------+---+------+---+------+------+ - */ -static void disas_simd_ext(DisasContext *s, uint32_t insn) -{ - int is_q =3D extract32(insn, 30, 1); - int op2 =3D extract32(insn, 22, 2); - int imm4 =3D extract32(insn, 11, 4); - int rm =3D extract32(insn, 16, 5); - int rn =3D extract32(insn, 5, 5); - int rd =3D extract32(insn, 0, 5); - int pos =3D imm4 << 3; - TCGv_i64 tcg_resl, tcg_resh; - - if (op2 !=3D 0 || (!is_q && extract32(imm4, 3, 1))) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - tcg_resh =3D tcg_temp_new_i64(); - tcg_resl =3D tcg_temp_new_i64(); - - /* Vd gets bits starting at pos bits into Vm:Vn. This is - * either extracting 128 bits from a 128:128 concatenation, or - * extracting 64 bits from a 64:64 concatenation. - */ - if (!is_q) { - read_vec_element(s, tcg_resl, rn, 0, MO_64); - if (pos !=3D 0) { - read_vec_element(s, tcg_resh, rm, 0, MO_64); - tcg_gen_extract2_i64(tcg_resl, tcg_resl, tcg_resh, pos); - } - } else { - TCGv_i64 tcg_hh; - typedef struct { - int reg; - int elt; - } EltPosns; - EltPosns eltposns[] =3D { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; - EltPosns *elt =3D eltposns; - - if (pos >=3D 64) { - elt++; - pos -=3D 64; - } - - read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); - elt++; - read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); - elt++; - if (pos !=3D 0) { - tcg_gen_extract2_i64(tcg_resl, tcg_resl, tcg_resh, pos); - tcg_hh =3D tcg_temp_new_i64(); - read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); - tcg_gen_extract2_i64(tcg_resh, tcg_resh, tcg_hh, pos); - } - } - - write_vec_element(s, tcg_resl, rd, 0, MO_64); - if (is_q) { - write_vec_element(s, tcg_resh, rd, 1, MO_64); - } - clear_vec_high(s, is_q, rd); -} - /* TBL/TBX * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 = 0 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+---= ---+ @@ -11860,7 +11836,6 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, { 0x0e000000, 0xbf208c00, disas_simd_tb }, { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, - { 0x2e000000, 0xbf208400, disas_simd_ext }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 62df4c4ceb..f72f95865f 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1136,3 +1136,8 @@ FMADD 0001 1111 .. 0 ..... 0 ..... ..... ..= ... @rrrr_hsd FMSUB 0001 1111 .. 0 ..... 1 ..... ..... ..... @rrrr_hsd FNMADD 0001 1111 .. 1 ..... 0 ..... ..... ..... @rrrr_hsd FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd + +# Advanced SIMD Extract + +EXT_d 0010 1110 00 0 rm:5 00 imm:3 0 rn:5 rd:5 +EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 rd:5 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109192; cv=none; d=zohomail.com; s=zohoarc; b=GsjdLn8IhnNgBNyCPE1DZyee0lB0ZYC/nBj30PXIk065yBdCb3jCQ1DCqLOD1s7Uqkcdb4h36gDKkuEi0wnuhxZZLx1CuwRx4B/4fdjk3Sg7JIXcR6F0e7VBqfGI8m6/9IoQyZz58v1SiwUSFe/NZIeeOTJDE2Ip4Wb0V3oyGtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109192; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=40qRQiWPnzwQZNkzfC9uwjfmjEELssT5eDCBB5PE7FA=; b=Gip7Ezh00x+7YqeJSpLArs5YLltDnyJlHQh6auqL2CNNBWYT/Ogh3TEPmYJjCBV+os99Wr2M5YgBYEGzkkDlAXd3Jy/KJJd3s7ZxtdO3Y+hPDzJzhmQ3SH78iW8NSEx0oOS0cupqRzTibnAnvq0ZMOk/z3r5G4MuyHVwDHV/b6Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109192705235.31311914126206; Wed, 11 Sep 2024 19:46:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm4-0003KE-IH; Wed, 11 Sep 2024 22:41:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlu-0002fS-N2 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:27 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZls-000498-PY for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:26 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-207397d1000so12569715ad.0 for ; Wed, 11 Sep 2024 19:41:24 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108883; x=1726713683; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=40qRQiWPnzwQZNkzfC9uwjfmjEELssT5eDCBB5PE7FA=; b=g2mRUJsqbtnhFzdCr/mZbMid5hJ5k5WCgLBqLcKMahAzu72wdSbY5CZ2qwvveW2pwX i0xTiSz7ur+Tc0VG4XuC9BBx0LCdu1fY7AmeTFcKzVC8g+ovJ2orRKFxcKpnB+Upjkem +Ng1Vr+e1d75ULV8XwTmgy+kbR5bSkxCyZ1iBPbjeHZQ4Ju4Z8A/UyXgTjAMNVV5wgAO NBTm2r9Fy0x8CAWlysgcvUwC7OSIA8LHhtiqK5chVZ1QHotSepMkAHpgmUHYXpJArMRN M64V3JIX6B8O37EtIh2DsX4/B6Ca9uYz/3DZ5fFAd9HqWQSNz+83EhL/OM5foDo+xubh v7kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108883; x=1726713683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=40qRQiWPnzwQZNkzfC9uwjfmjEELssT5eDCBB5PE7FA=; b=ox39j//cCi8U1QzM96b/S80ySw/rUGsIkv7Aquu+QxEWDY4eFM54+iModaTiN2rJQr NEB+TJu5NppPetjk3sFWpKRrkFfQJVc1FCvkxSD+9/W9dDeu+vJN9NV5lhUFUmLZbaG2 e0oGA6IrOULSoEXC4ZjpjXqXZBq1htXV7XewrAmO8msuTV7gUqNGsTDcMlEl/XkUw1el ckNg4m9Tib9ucRb2j0gn97QJUqz849xHm6wBJjZDZ8Ikd3KCfxtv0rYkkla670VKaQt3 h0B+huhBIkvk+BnKB1jpYOxLNp/8kIA0mrD2S9J6TFFQegsBxNy9OKIVRcMZl6FtnKUU Ct7Q== X-Gm-Message-State: AOJu0Ywd2y5/QeKOYeETF+nSWUBvUjnhgFxAzlOEtF9X94s9iuSxlRwv /C+jasm60FApMvfHXgYAhEQcSqZyEXEbXuLkZLwz/SYrsrFCM5SaucS5hKlXnNxEm9qVwJe/U23 5 X-Google-Smtp-Source: AGHT+IE3eduu1BYBTvNNRqEtBqAYJGdkcgfDcnWoAG7anlJoj9OzJKnXLxwQanGTr5xuzvjiMbKPsQ== X-Received: by 2002:a17:902:f542:b0:206:9dfb:3e9e with SMTP id d9443c01a7336-2074c5eebbdmr88259105ad.10.1726108882950; Wed, 11 Sep 2024 19:41:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 07/29] target/arm: Convert TBL, TBX to decodetree Date: Wed, 11 Sep 2024 19:40:52 -0700 Message-ID: <20240912024114.1097832-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109193675116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 47 ++++++++++------------------------ target/arm/tcg/a64.decode | 4 +++ 2 files changed, 18 insertions(+), 33 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 48188d4116..70173c67c2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4680,6 +4680,20 @@ static bool trans_EXTR(DisasContext *s, arg_extract = *a) return true; } =20 +static bool trans_TBL_TBX(DisasContext *s, arg_TBL_TBX *a) +{ + if (fp_access_check(s)) { + int len =3D (a->len + 1) * 16; + + tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rm), tcg_env, + a->q ? 16 : 8, vec_full_reg_size(s), + (len << 6) | (a->tbx << 5) | a->rn, + gen_helper_simd_tblx); + } + return true; +} + /* * Cryptographic AES, SHA, SHA512 */ @@ -8938,38 +8952,6 @@ static void disas_data_proc_fp(DisasContext *s, uint= 32_t insn) } } =20 -/* TBL/TBX - * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 = 0 - * +---+---+-------------+-----+---+------+---+-----+----+-----+------+---= ---+ - * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | R= d | - * +---+---+-------------+-----+---+------+---+-----+----+-----+------+---= ---+ - */ -static void disas_simd_tb(DisasContext *s, uint32_t insn) -{ - int op2 =3D extract32(insn, 22, 2); - int is_q =3D extract32(insn, 30, 1); - int rm =3D extract32(insn, 16, 5); - int rn =3D extract32(insn, 5, 5); - int rd =3D extract32(insn, 0, 5); - int is_tbx =3D extract32(insn, 12, 1); - int len =3D (extract32(insn, 13, 2) + 1) * 16; - - if (op2 !=3D 0) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), - vec_full_reg_offset(s, rm), tcg_env, - is_q ? 16 : 8, vec_full_reg_size(s), - (len << 6) | (is_tbx << 5) | rn, - gen_helper_simd_tblx); -} - /* ZIP/UZP/TRN * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 * +---+---+-------------+------+---+------+---+------------------+------+ @@ -11834,7 +11816,6 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede = it */ { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, - { 0x0e000000, 0xbf208c00, disas_simd_tb }, { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f72f95865f..e2a3ef62ef 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1141,3 +1141,7 @@ FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..= ... @rrrr_hsd =20 EXT_d 0010 1110 00 0 rm:5 00 imm:3 0 rn:5 rd:5 EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 rd:5 + +# Advanced SIMD Table Lookup + +TBL_TBX 0 q:1 00 1110 000 rm:5 0 len:2 tbx:1 00 rn:5 rd:5 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109020; cv=none; d=zohomail.com; s=zohoarc; b=OpFMHeXHEC4WHueUC4NXhL3Lhz6hKGxHIv5x8ctnnlaeQRz+V1FMFMri1XHLd4gRtJrQ2YcF00RU+NGeCBVhaQVz37qhJ9ZvkHjSvg/lQtPLT35Ru1EYlZfnZcrozm4RyyGCvvs3Piz+WrzU6oPZrpZTlMscq6Mv3R3s9/FaIIU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109020; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gBoCnQOSiyLDfGRfoss5cPWPIDkrcq94UK7ozrO98a4=; b=Dl6qf1DvR2eKF6k8DPJXKEdf7Gs7PUNoLdcvRaQs8chY99p69QqQb0tOJ0fDD0hq8shquaJpseWSfcKVMdqdb2/vCboTAyulWusbDjKgphZ0RX4QmTd+kNJnAM0bIJihPHmJxwTJKK+is64ywmK8t41QQvmMGlUaK3/YuGErjcE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109020668310.14521449477013; Wed, 11 Sep 2024 19:43:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZmA-0003l5-2o; Wed, 11 Sep 2024 22:41:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlv-0002hj-9C for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:27 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlt-00049R-AR for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:26 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2053f6b8201so4517195ad.2 for ; Wed, 11 Sep 2024 19:41:24 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108884; x=1726713684; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gBoCnQOSiyLDfGRfoss5cPWPIDkrcq94UK7ozrO98a4=; b=dsB6eTUcObJXFV+Cm2jOjJTkZGpGBf5IUrWxq7UsPF2tZlsCh/DUzmjwv1A8eGlUN3 qGu/fN8XwKCzWhtkJnVEQrC38elE3vB7ekAA4bWbEvrWw557OpHV3qopE0/xT6438hzr w2k0G6Znki2CWSY4Vqw33/M6YGcHg+1u0lxrxkqj8a55Dj+1bWFHdXvNykvLzenpWPIg T0XNR+UXxs7eYJyWIFKRdise3bMq9Ty9si+YiuIvpmYtt5V21LmOz1saAIL1o+kbTByt n5QsKkw5ufey4wdRbGLBw+HMfsYb7XLX/wy9NkrTKTSAyl3/GGadJjofq1nDfLKlFBWZ NWfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108884; x=1726713684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109021234116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 158 ++++++++++++++------------------- target/arm/tcg/a64.decode | 9 ++ 2 files changed, 77 insertions(+), 90 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 70173c67c2..04160b2513 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4694,6 +4694,74 @@ static bool trans_TBL_TBX(DisasContext *s, arg_TBL_T= BX *a) return true; } =20 +typedef int simd_permute_idx_fn(int i, int part, int elements); + +static bool do_simd_permute(DisasContext *s, arg_qrrr_e *a, + simd_permute_idx_fn *fn, int part) +{ + MemOp esz =3D a->esz; + int datasize =3D a->q ? 16 : 8; + int elements =3D datasize >> esz; + TCGv_i64 tcg_res[2], tcg_ele; + + if (esz =3D=3D MO_64 && !a->q) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + tcg_res[0] =3D tcg_temp_new_i64(); + tcg_res[1] =3D a->q ? tcg_temp_new_i64() : NULL; + tcg_ele =3D tcg_temp_new_i64(); + + for (int i =3D 0; i < elements; i++) { + int o, w, idx; + + idx =3D fn(i, part, elements); + read_vec_element(s, tcg_ele, (idx & elements ? a->rm : a->rn), + idx & (elements - 1), esz); + + w =3D (i << (esz + 3)) / 64; + o =3D (i << (esz + 3)) % 64; + if (o =3D=3D 0) { + tcg_gen_mov_i64(tcg_res[w], tcg_ele); + } else { + tcg_gen_deposit_i64(tcg_res[w], tcg_res[w], tcg_ele, o, 8 << e= sz); + } + } + + for (int i =3D a->q; i >=3D 0; --i) { + write_vec_element(s, tcg_res[i], a->rd, i, MO_64); + } + clear_vec_high(s, a->q, a->rd); + return true; +} + +static int permute_load_uzp(int i, int part, int elements) +{ + return 2 * i + part; +} + +TRANS(UZP1, do_simd_permute, a, permute_load_uzp, 0) +TRANS(UZP2, do_simd_permute, a, permute_load_uzp, 1) + +static int permute_load_trn(int i, int part, int elements) +{ + return (i & 1) * elements + (i & ~1) + part; +} + +TRANS(TRN1, do_simd_permute, a, permute_load_trn, 0) +TRANS(TRN2, do_simd_permute, a, permute_load_trn, 1) + +static int permute_load_zip(int i, int part, int elements) +{ + return (i & 1) * elements + ((part * elements + i) >> 1); +} + +TRANS(ZIP1, do_simd_permute, a, permute_load_zip, 0) +TRANS(ZIP2, do_simd_permute, a, permute_load_zip, 1) + /* * Cryptographic AES, SHA, SHA512 */ @@ -8952,95 +9020,6 @@ static void disas_data_proc_fp(DisasContext *s, uint= 32_t insn) } } =20 -/* ZIP/UZP/TRN - * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 - * +---+---+-------------+------+---+------+---+------------------+------+ - * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | - * +---+---+-------------+------+---+------+---+------------------+------+ - */ -static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) -{ - int rd =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 22, 2); - /* opc field bits [1:0] indicate ZIP/UZP/TRN; - * bit 2 indicates 1 vs 2 variant of the insn. - */ - int opcode =3D extract32(insn, 12, 2); - bool part =3D extract32(insn, 14, 1); - bool is_q =3D extract32(insn, 30, 1); - int esize =3D 8 << size; - int i; - int datasize =3D is_q ? 128 : 64; - int elements =3D datasize / esize; - TCGv_i64 tcg_res[2], tcg_ele; - - if (opcode =3D=3D 0 || (size =3D=3D 3 && !is_q)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - tcg_res[0] =3D tcg_temp_new_i64(); - tcg_res[1] =3D is_q ? tcg_temp_new_i64() : NULL; - tcg_ele =3D tcg_temp_new_i64(); - - for (i =3D 0; i < elements; i++) { - int o, w; - - switch (opcode) { - case 1: /* UZP1/2 */ - { - int midpoint =3D elements / 2; - if (i < midpoint) { - read_vec_element(s, tcg_ele, rn, 2 * i + part, size); - } else { - read_vec_element(s, tcg_ele, rm, - 2 * (i - midpoint) + part, size); - } - break; - } - case 2: /* TRN1/2 */ - if (i & 1) { - read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size); - } else { - read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size); - } - break; - case 3: /* ZIP1/2 */ - { - int base =3D part * elements / 2; - if (i & 1) { - read_vec_element(s, tcg_ele, rm, base + (i >> 1), size); - } else { - read_vec_element(s, tcg_ele, rn, base + (i >> 1), size); - } - break; - } - default: - g_assert_not_reached(); - } - - w =3D (i * esize) / 64; - o =3D (i * esize) % 64; - if (o =3D=3D 0) { - tcg_gen_mov_i64(tcg_res[w], tcg_ele); - } else { - tcg_gen_shli_i64(tcg_ele, tcg_ele, o); - tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele); - } - } - - for (i =3D 0; i <=3D is_q; ++i) { - write_vec_element(s, tcg_res[i], rd, i, MO_64); - } - clear_vec_high(s, is_q, rd); -} - /* * do_reduction_op helper * @@ -11816,7 +11795,6 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede = it */ { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, - { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e2a3ef62ef..7f71c56f83 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1145,3 +1145,12 @@ EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 = rd:5 # Advanced SIMD Table Lookup =20 TBL_TBX 0 q:1 00 1110 000 rm:5 0 len:2 tbx:1 00 rn:5 rd:5 + +# Advanced SIMD Permute + +UZP1 0.00 1110 .. 0 ..... 0 001 10 ..... ..... @qrrr_e +UZP2 0.00 1110 .. 0 ..... 0 101 10 ..... ..... @qrrr_e +TRN1 0.00 1110 .. 0 ..... 0 010 10 ..... ..... @qrrr_e +TRN2 0.00 1110 .. 0 ..... 0 110 10 ..... ..... @qrrr_e +ZIP1 0.00 1110 .. 0 ..... 0 011 10 ..... ..... @qrrr_e +ZIP2 0.00 1110 .. 0 ..... 0 111 10 ..... ..... @qrrr_e --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108885; x=1726713685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=htF5qh+BwrQAazett+74anTVYDcrx88zDGCrAO2eD7Q=; b=zEwKls3DyIInNlLldxJGMvfd73Aiw/7LX6w0tr/oEfv8eRNdDS1XdTbq/o7UPIJWvG G7KW0D3Y9N3Y1WShUWDjsJ+3zYNE5qgWQYTTp48rDqo+Cz9cuG8JLNsTApgCzRhd2SPT hEhcnWPVLj0M57zDYWYtnaC21KlND5SCe26uTYKztHe4blY7/7LeIcehdsGSgKwUHgKA jAlU/NWOXmI39x9AN5WYuOsbNQO+9bJaplFreIJbq2PBPUSzFlGpmvhgkUje4we2V+pp 2T9ShhTIvM6AubkwChPvwpcOsGdxD3oXwWI8ze8tKjJvnXkxXM78s2bQWbzK2o0vIG0L Ji2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108885; x=1726713685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=htF5qh+BwrQAazett+74anTVYDcrx88zDGCrAO2eD7Q=; b=PWdd1KHPcds3GDrGUnNa0Fy/WXqinys+X4ysYSSQQFdPb04UwYskaWcAjdXW5v0gyN mCZSPxNpkKDjZbvgq434Reg2rI5XowJoMwrc3YPygtyiAn1VF4CgnSRnYFqXWuSoYk9c J0pc6ScYBfV0BnUON3oeqU15H7vbmFBE+CofVPxkBGIVvBFkudUUFCoWDHbebR/do6OV vSSKmnPnn9Dzj2cvLgNvc712gHVTmQFmlBZ89MQOff9x9lPAZqIK6tSCTv1MpWMcYqK1 1T5FMxT2DipIM/cLmI7r8ZjiqkrplneNB2jPLRyyZ1p0f7tdtgOCxWijotevIT1BZPPm 420w== X-Gm-Message-State: AOJu0YwK3nNsi1tgBiqAhQkaqCWH7b04rYU1DNHFq78E8VzVYK4b91gx pX9CIPeDLOQDdTMDjcijVvQ04E1PVQKpoU/58Vrdgl8WJdS3ACrsTbm3/ntcyLWHvhJ/RHqotaB / X-Google-Smtp-Source: AGHT+IGvHG5b7yffNEcxCesGgbdGY3zf4uQfQNzZsJs9bSbmsUeJ3V9sQggPGINEQGUgwT5M+li8vw== X-Received: by 2002:a17:902:d4c1:b0:205:913b:d9ad with SMTP id d9443c01a7336-2076d6268ffmr17109915ad.0.1726108884628; Wed, 11 Sep 2024 19:41:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/29] target/arm: Simplify do_reduction_op Date: Wed, 11 Sep 2024 19:40:54 -0700 Message-ID: <20240912024114.1097832-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108988897116600 Content-Type: text/plain; charset="utf-8" Use simple shift and add instead of ctpop, ctz, shift and mask. Unlike SVE, there is no predicate to disable elements. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 40 +++++++++++----------------------- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 04160b2513..74efb35164 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -9027,34 +9027,23 @@ static void disas_data_proc_fp(DisasContext *s, uin= t32_t insn) * important for correct NaN propagation that we do these * operations in exactly the order specified by the pseudocode. * - * This is a recursive function, TCG temps should be freed by the - * calling function once it is done with the values. + * This is a recursive function. */ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, - int esize, int size, int vmap, TCGv_ptr fp= st) + MemOp esz, int ebase, int ecount, TCGv_ptr= fpst) { - if (esize =3D=3D size) { - int element; - MemOp msize =3D esize =3D=3D 16 ? MO_16 : MO_32; - TCGv_i32 tcg_elem; - - /* We should have one register left here */ - assert(ctpop8(vmap) =3D=3D 1); - element =3D ctz32(vmap); - assert(element < 8); - - tcg_elem =3D tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_elem, rn, element, msize); + if (ecount =3D=3D 1) { + TCGv_i32 tcg_elem =3D tcg_temp_new_i32(); + read_vec_element_i32(s, tcg_elem, rn, ebase, esz); return tcg_elem; } else { - int bits =3D size / 2; - int shift =3D ctpop8(vmap) / 2; - int vmap_lo =3D (vmap >> shift) & vmap; - int vmap_hi =3D (vmap & ~vmap_lo); + int half =3D ecount >> 1; TCGv_i32 tcg_hi, tcg_lo, tcg_res; =20 - tcg_hi =3D do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, = fpst); - tcg_lo =3D do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, = fpst); + tcg_hi =3D do_reduction_op(s, fpopcode, rn, esz, + ebase + half, half, fpst); + tcg_lo =3D do_reduction_op(s, fpopcode, rn, esz, + ebase, half, fpst); tcg_res =3D tcg_temp_new_i32(); =20 switch (fpopcode) { @@ -9105,7 +9094,6 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) bool is_u =3D extract32(insn, 29, 1); bool is_fp =3D false; bool is_min =3D false; - int esize; int elements; int i; TCGv_i64 tcg_res, tcg_elt; @@ -9152,8 +9140,7 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) return; } =20 - esize =3D 8 << size; - elements =3D (is_q ? 128 : 64) / esize; + elements =3D (is_q ? 16 : 8) >> size; =20 tcg_res =3D tcg_temp_new_i64(); tcg_elt =3D tcg_temp_new_i64(); @@ -9208,9 +9195,8 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) */ TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); int fpopcode =3D opcode | is_min << 4 | is_u << 5; - int vmap =3D (1 << elements) - 1; - TCGv_i32 tcg_res32 =3D do_reduction_op(s, fpopcode, rn, esize, - (is_q ? 128 : 64), vmap, fpst= ); + TCGv_i32 tcg_res32 =3D do_reduction_op(s, fpopcode, rn, size, + 0, elements, fpst); tcg_gen_extu_i32_i64(tcg_res, tcg_res32); } =20 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109075; cv=none; d=zohomail.com; s=zohoarc; b=fpajPOREk3YYS74kZNuvnYnHLawNofDXo+g8J3wZHeL6dHxX788Dhd/5NxkfI53UMLm7U3p/u5zfJ72cDwW9OfiD5e4bsT3Ecrg7XeJb8ezImcb40L0a9Qis3VOK/cOT2oz7nsVlQNLxfArQH52+RjnsZUlExkb5/aT8c+dFqVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109075; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AiXgo5C5iMvrCSwZrTjjoeF1dyYuwPhkfLCjH211bC8=; b=ai7sPi9U9xc2o+2i48NivTjOktyfwU/W4G/NK3ecZGSrJKktOyPocs9k5Bqudge+wXiaOu2FUDLEl+vtFdqdc61jD0tAMBhRNy0nkinG9xi2QKS+9r9132T7gsToyyI4hPw7pa/Gex7mS67QAtqxu9M0hgpq/S/XNyyvX/+npgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109075810681.8259344731213; Wed, 11 Sep 2024 19:44:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm8-0003aJ-Bl; Wed, 11 Sep 2024 22:41:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlx-0002rC-OQ for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:29 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlv-0004AB-0c for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:29 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-20696938f86so3980995ad.3 for ; Wed, 11 Sep 2024 19:41:26 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108885; x=1726713685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AiXgo5C5iMvrCSwZrTjjoeF1dyYuwPhkfLCjH211bC8=; b=rP+z8QqhNtJ6Ymr4OE4DyBNtnFDV3e+Vl+DTDGOopXcui0q+xdj1hRS+8DkaXfE2lk ZeAMP++muj1eWrwmZH1YCpJpoqRcGID9CxI/a5Fjm10ZKGwnGZVA9ZZGV+CwIRgYb9tp K6eJMBQcjvXM1L0h0yCva6/iR+zRXyB18fx5RN9SsR1r6IGMN6pw8qFcQsem6IiRmFaG GjCT9GzKOs5GfvKBPFEF3AE+K5E7e9/fIIMIvIkyRgelYSeSUWkHlR7fqxeOTTigfDZ7 ESWtUeW2LAqDwPaCFzbCZCyxwOApZGrzGFm7SdZsZcn+U/XnF+HzhMsHKqe/zhe53Miz mAvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108885; x=1726713685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AiXgo5C5iMvrCSwZrTjjoeF1dyYuwPhkfLCjH211bC8=; b=Oa2wsjWOtHRTisMRzCbcmCxo7RCprM8L03Q/U4rdCZJ1zfbT/zixEvR9ik8FRuEyQq lAMeITjyi58twSWaCv2FWXRYmi4iernYBJW5n3EO9IkvFuZ9AXyLruKB0meYF/Dw9fTl Trspm3w7efHgx5Vqc9nt9yb0MYdYkZe+s50oGBlRTquyKTPGSBhHViyrcHX/IpMMSglx c+QxYERaARYlyg/nydukzPmy1FBZMz+O7hmnlfR/6hSlfd7s4bp4W46QPJnHisO5Plrt 0ceq8QWy1HFNgnGs91IOBoHX6dcDjZStf8aUFoyFY6WU28XmH2lVBFZqiNGNOQN2CgWg C17Q== X-Gm-Message-State: AOJu0Yy7nD/TpYedC2HlOf3ABG6K4/I0VkTVgoX0luyVeQ3Flel2mONY A1eUN7MPD5Zjjk63vT9Q12g0RsEhfAIK60t7OoPPvCXFdUMgbobR89/b7RWEtQuCHQdLLrFbJln K X-Google-Smtp-Source: AGHT+IFq7YzFJpDMFvWjfjFDEN7FmahiDiVwqWQ4zcRXRZMxg45tV6TXdpZemcziIst2QOSwwT9vEw== X-Received: by 2002:a17:903:22c1:b0:207:3a5e:8809 with SMTP id d9443c01a7336-2076e43efbbmr18620575ad.49.1726108885328; Wed, 11 Sep 2024 19:41:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/29] target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree Date: Wed, 11 Sep 2024 19:40:55 -0700 Message-ID: <20240912024114.1097832-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109077279116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 140 ++++++++++++--------------------- target/arm/tcg/a64.decode | 12 +++ 2 files changed, 61 insertions(+), 91 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 74efb35164..593a1774d8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6794,6 +6794,47 @@ TRANS(FNMADD, do_fmadd, a, true, true) TRANS(FMSUB, do_fmadd, a, false, true) TRANS(FNMSUB, do_fmadd, a, true, false) =20 +/* + * Advanced SIMD Across Lanes + */ + +static bool do_int_reduction(DisasContext *s, arg_qrr_e *a, bool widen, + MemOp src_sign, NeonGenTwo64OpFn *fn) +{ + TCGv_i64 tcg_res, tcg_elt; + MemOp src_mop =3D a->esz | src_sign; + int elements =3D (a->q ? 16 : 8) >> a->esz; + + /* Reject MO_64, and MO_32 without Q: a minimum of 4 elements. */ + if (elements < 4) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + tcg_res =3D tcg_temp_new_i64(); + tcg_elt =3D tcg_temp_new_i64(); + + read_vec_element(s, tcg_res, a->rn, 0, src_mop); + for (int i =3D 1; i < elements; i++) { + read_vec_element(s, tcg_elt, a->rn, i, src_mop); + fn(tcg_res, tcg_res, tcg_elt); + } + + tcg_gen_ext_i64(tcg_res, tcg_res, a->esz + widen); + write_fp_dreg(s, a->rd, tcg_res); + return true; +} + +TRANS(ADDV, do_int_reduction, a, false, 0, tcg_gen_add_i64) +TRANS(SADDLV, do_int_reduction, a, true, MO_SIGN, tcg_gen_add_i64) +TRANS(UADDLV, do_int_reduction, a, true, 0, tcg_gen_add_i64) +TRANS(SMAXV, do_int_reduction, a, false, MO_SIGN, tcg_gen_smax_i64) +TRANS(UMAXV, do_int_reduction, a, false, 0, tcg_gen_umax_i64) +TRANS(SMINV, do_int_reduction, a, false, MO_SIGN, tcg_gen_smin_i64) +TRANS(UMINV, do_int_reduction, a, false, 0, tcg_gen_umin_i64) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9092,27 +9133,10 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) int opcode =3D extract32(insn, 12, 5); bool is_q =3D extract32(insn, 30, 1); bool is_u =3D extract32(insn, 29, 1); - bool is_fp =3D false; bool is_min =3D false; int elements; - int i; - TCGv_i64 tcg_res, tcg_elt; =20 switch (opcode) { - case 0x1b: /* ADDV */ - if (is_u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x3: /* SADDLV, UADDLV */ - case 0xa: /* SMAXV, UMAXV */ - case 0x1a: /* SMINV, UMINV */ - if (size =3D=3D 3 || (size =3D=3D 2 && !is_q)) { - unallocated_encoding(s); - return; - } - break; case 0xc: /* FMAXNMV, FMINNMV */ case 0xf: /* FMAXV, FMINV */ /* Bit 1 of size field encodes min vs max and the actual size @@ -9121,7 +9145,6 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) * precision. */ is_min =3D extract32(size, 1, 1); - is_fp =3D true; if (!is_u && dc_isar_feature(aa64_fp16, s)) { size =3D 1; } else if (!is_u || !is_q || extract32(size, 0, 1)) { @@ -9132,6 +9155,10 @@ static void disas_simd_across_lanes(DisasContext *s,= uint32_t insn) } break; default: + case 0x3: /* SADDLV, UADDLV */ + case 0xa: /* SMAXV, UMAXV */ + case 0x1a: /* SMINV, UMINV */ + case 0x1b: /* ADDV */ unallocated_encoding(s); return; } @@ -9142,52 +9169,7 @@ static void disas_simd_across_lanes(DisasContext *s,= uint32_t insn) =20 elements =3D (is_q ? 16 : 8) >> size; =20 - tcg_res =3D tcg_temp_new_i64(); - tcg_elt =3D tcg_temp_new_i64(); - - /* These instructions operate across all lanes of a vector - * to produce a single result. We can guarantee that a 64 - * bit intermediate is sufficient: - * + for [US]ADDLV the maximum element size is 32 bits, and - * the result type is 64 bits - * + for FMAX*V, FMIN*V, ADDV the intermediate type is the - * same as the element size, which is 32 bits at most - * For the integer operations we can choose to work at 64 - * or 32 bits and truncate at the end; for simplicity - * we use 64 bits always. The floating point - * ops do require 32 bit intermediates, though. - */ - if (!is_fp) { - read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); - - for (i =3D 1; i < elements; i++) { - read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN= )); - - switch (opcode) { - case 0x03: /* SADDLV / UADDLV */ - case 0x1b: /* ADDV */ - tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); - break; - case 0x0a: /* SMAXV / UMAXV */ - if (is_u) { - tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt); - } else { - tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt); - } - break; - case 0x1a: /* SMINV / UMINV */ - if (is_u) { - tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt); - } else { - tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt); - } - break; - default: - g_assert_not_reached(); - } - - } - } else { + { /* Floating point vector reduction ops which work across 32 * bit (single) or 16 bit (half-precision) intermediates. * Note that correct NaN propagation requires that we do these @@ -9195,34 +9177,10 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) */ TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); int fpopcode =3D opcode | is_min << 4 | is_u << 5; - TCGv_i32 tcg_res32 =3D do_reduction_op(s, fpopcode, rn, size, - 0, elements, fpst); - tcg_gen_extu_i32_i64(tcg_res, tcg_res32); + TCGv_i32 tcg_res =3D do_reduction_op(s, fpopcode, rn, size, + 0, elements, fpst); + write_fp_sreg(s, rd, tcg_res); } - - /* Now truncate the result to the width required for the final output = */ - if (opcode =3D=3D 0x03) { - /* SADDLV, UADDLV: result is 2*esize */ - size++; - } - - switch (size) { - case 0: - tcg_gen_ext8u_i64(tcg_res, tcg_res); - break; - case 1: - tcg_gen_ext16u_i64(tcg_res, tcg_res); - break; - case 2: - tcg_gen_ext32u_i64(tcg_res, tcg_res); - break; - case 3: - break; - default: - g_assert_not_reached(); - } - - write_fp_dreg(s, rd, tcg_res); } =20 /* AdvSIMD modified immediate diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 7f71c56f83..5ab4b11781 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -59,6 +59,8 @@ @rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=3D1 esz= =3D3 @rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=3D1 esz= =3D3 =20 +@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e + @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=3D0 @qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=3D1 @qrrr_s . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=3D2 @@ -1154,3 +1156,13 @@ TRN1 0.00 1110 .. 0 ..... 0 010 10 ..... = ..... @qrrr_e TRN2 0.00 1110 .. 0 ..... 0 110 10 ..... ..... @qrrr_e ZIP1 0.00 1110 .. 0 ..... 0 011 10 ..... ..... @qrrr_e ZIP2 0.00 1110 .. 0 ..... 0 111 10 ..... ..... @qrrr_e + +# Advanced SIMD Across Lanes + +ADDV 0.00 1110 .. 11000 11011 10 ..... ..... @qrr_e +SADDLV 0.00 1110 .. 11000 00011 10 ..... ..... @qrr_e +UADDLV 0.10 1110 .. 11000 00011 10 ..... ..... @qrr_e +SMAXV 0.00 1110 .. 11000 01010 10 ..... ..... @qrr_e +UMAXV 0.10 1110 .. 11000 01010 10 ..... ..... @qrr_e +SMINV 0.00 1110 .. 11000 11010 10 ..... ..... @qrr_e +UMINV 0.10 1110 .. 11000 11010 10 ..... ..... @qrr_e --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109042; cv=none; d=zohomail.com; s=zohoarc; b=OJqjLZi/Rogz8MyGxeeOowm0iDYCaBSv5sz4fhFDsXyd4pjDNed5RtjSFqizvASOwlNDKbs7NcQ4gwS7+aBHhe3N4ubGmlGGlpnUQImVVNdmyq6cCV9mRSXZ1Ykd9W37S0A54L4FGQSE6O3V8A94ZqG5EkaKl9lhdyoqV6FDHvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109042; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=y+M/vrV0uMNpf4dh4yRfZZht1RPv8tvP+7CoYBlpT8w=; b=jiiGRovxqwJVANXAwUrnOw67Jwv94mvM9Gzypwvt+e3sc/dHcr86usOSp98ft/VRIZhgT5X4J7zxK6Tkw8Qe2RcjGwIJv0rqdgGayxsOQRgHN46l4NkCTnVN84/78dbXkT9BnWg8ckCmsLZxkurBMf1jn1/P/Mh7w6xt/iSAFYM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109042816223.26683784740976; Wed, 11 Sep 2024 19:44:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm6-0003Rq-A8; Wed, 11 Sep 2024 22:41:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlx-0002rw-V9 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:29 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlv-0004AU-LB for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:29 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2068acc8b98so4717565ad.3 for ; Wed, 11 Sep 2024 19:41:27 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108886; x=1726713686; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y+M/vrV0uMNpf4dh4yRfZZht1RPv8tvP+7CoYBlpT8w=; b=FzQ21tVoLqGkjfvExo4tMvGgKbdd9QIHSmaMvnAnAUeT6UMM4iRdcPJIK/hrgYA3g8 cBUEV0xjOBibOHDP2Ar0ujTOOtUEJbvw+ind7L92PX1Mi81memExewy7ka8ZGKZN+tH8 0CQix/c5ZwMpQ40bcK6efAt6jjQ29rnQSr3hh+zVsgRgOrXOnxTBU/RO/oJ1G/pysuec yXGyLLzGCVwrh/weqgqfkNL9/ImQYEUYp5vMfzUC29dSmvxITgswHGvgN4e4/buB698v sYzVcT7BAjWyYekNQal1N+nu0rTrgu6qDOj6ndOpKQ1kkVTuuE+QZ0o4nPRcAJ09wjc6 y6YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108886; x=1726713686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y+M/vrV0uMNpf4dh4yRfZZht1RPv8tvP+7CoYBlpT8w=; b=nUB64IDQxN0665LnX1J0QWQRN05ihouXXY/ol0WV4sbfhVa3fTmpfA09a60dzDt55W KTQF4zeX6db6ThCChgEhPS6pc4jFxu4bpwm0/cBIMFwA5Gb9LA05UdZ28S0/DeS0FJKo vI8Qf7J1gXATXJ4bZbCE1NPMBfNpiP4TQLXbrrDsJy53pHLldricEyJnCUe+I5kB18Hg 2Tnj3rW55iFMRaH6CGN9iG+f8U8d6kCtW0z1yICbrawINvTonB4w/7o0+FZePYqcUdfu SKnw7w5qGRgo7yE1pn3Pnv9ubQQEqlEGAB0EttdWxIadIdy/MKd1uiUiqRm3GYmLl5T8 xy3Q== X-Gm-Message-State: AOJu0YyQMx4KydmYxkN2I0ddBYH1poZ3FsRFKdu0Mku1GW5cNtlN07vI D7QJFXCRawRxt7xefOPd9TrPLg8cQqz7O6Bnt31c6zZGUae0If/iG1Z83ZA/e0RyuwI79JowvfT G X-Google-Smtp-Source: AGHT+IEW3y4LiXLwQzICFx9C+st1Z4M/l4aUT6Y2yrNzIJy37NJHvy+caPea6n8dBgKhskF/uGAtnA== X-Received: by 2002:a17:903:185:b0:205:8425:e9c6 with SMTP id d9443c01a7336-2076e43fe94mr15282055ad.52.1726108886228; Wed, 11 Sep 2024 19:41:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 11/29] target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree Date: Wed, 11 Sep 2024 19:40:56 -0700 Message-ID: <20240912024114.1097832-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109043135116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 176 ++++++++++----------------------- target/arm/tcg/a64.decode | 14 +++ 2 files changed, 67 insertions(+), 123 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 593a1774d8..aec2f6a542 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6835,6 +6835,59 @@ TRANS(UMAXV, do_int_reduction, a, false, 0, tcg_gen_= umax_i64) TRANS(SMINV, do_int_reduction, a, false, MO_SIGN, tcg_gen_smin_i64) TRANS(UMINV, do_int_reduction, a, false, 0, tcg_gen_umin_i64) =20 +/* + * do_fp_reduction helper + * + * This mirrors the Reduce() pseudocode in the ARM ARM. It is + * important for correct NaN propagation that we do these + * operations in exactly the order specified by the pseudocode. + * + * This is a recursive function. + */ +static TCGv_i32 do_reduction_op(DisasContext *s, int rn, MemOp esz, + int ebase, int ecount, TCGv_ptr fpst, + NeonGenTwoSingleOpFn *fn) +{ + if (ecount =3D=3D 1) { + TCGv_i32 tcg_elem =3D tcg_temp_new_i32(); + read_vec_element_i32(s, tcg_elem, rn, ebase, esz); + return tcg_elem; + } else { + int half =3D ecount >> 1; + TCGv_i32 tcg_hi, tcg_lo, tcg_res; + + tcg_hi =3D do_reduction_op(s, rn, esz, ebase + half, half, fpst, f= n); + tcg_lo =3D do_reduction_op(s, rn, esz, ebase, half, fpst, fn); + tcg_res =3D tcg_temp_new_i32(); + + fn(tcg_res, tcg_lo, tcg_hi, fpst); + return tcg_res; + } +} + +static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a, + NeonGenTwoSingleOpFn *fn) +{ + if (fp_access_check(s)) { + MemOp esz =3D a->esz; + int elts =3D (a->q ? 16 : 8) >> esz; + TCGv_ptr fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16 : = FPST_FPCR); + TCGv_i32 res =3D do_reduction_op(s, a->rn, esz, 0, elts, fpst, fn); + write_fp_sreg(s, a->rd, res); + } + return true; +} + +TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_ma= xnumh) +TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_mi= nnumh) +TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_maxh) +TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a, gen_helper_advsimd_minh) + +TRANS(FMAXNMV_s, do_fp_reduction, a, gen_helper_vfp_maxnums) +TRANS(FMINNMV_s, do_fp_reduction, a, gen_helper_vfp_minnums) +TRANS(FMAXV_s, do_fp_reduction, a, gen_helper_vfp_maxs) +TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9061,128 +9114,6 @@ static void disas_data_proc_fp(DisasContext *s, uin= t32_t insn) } } =20 -/* - * do_reduction_op helper - * - * This mirrors the Reduce() pseudocode in the ARM ARM. It is - * important for correct NaN propagation that we do these - * operations in exactly the order specified by the pseudocode. - * - * This is a recursive function. - */ -static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, - MemOp esz, int ebase, int ecount, TCGv_ptr= fpst) -{ - if (ecount =3D=3D 1) { - TCGv_i32 tcg_elem =3D tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_elem, rn, ebase, esz); - return tcg_elem; - } else { - int half =3D ecount >> 1; - TCGv_i32 tcg_hi, tcg_lo, tcg_res; - - tcg_hi =3D do_reduction_op(s, fpopcode, rn, esz, - ebase + half, half, fpst); - tcg_lo =3D do_reduction_op(s, fpopcode, rn, esz, - ebase, half, fpst); - tcg_res =3D tcg_temp_new_i32(); - - switch (fpopcode) { - case 0x0c: /* fmaxnmv half-precision */ - gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x0f: /* fmaxv half-precision */ - gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x1c: /* fminnmv half-precision */ - gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x1f: /* fminv half-precision */ - gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x2c: /* fmaxnmv */ - gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x2f: /* fmaxv */ - gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x3c: /* fminnmv */ - gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); - break; - case 0x3f: /* fminv */ - gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); - break; - default: - g_assert_not_reached(); - } - return tcg_res; - } -} - -/* AdvSIMD across lanes - * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 - * +---+---+---+-----------+------+-----------+--------+-----+------+-----= -+ - * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd = | - * +---+---+---+-----------+------+-----------+--------+-----+------+-----= -+ - */ -static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) -{ - int rd =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int size =3D extract32(insn, 22, 2); - int opcode =3D extract32(insn, 12, 5); - bool is_q =3D extract32(insn, 30, 1); - bool is_u =3D extract32(insn, 29, 1); - bool is_min =3D false; - int elements; - - switch (opcode) { - case 0xc: /* FMAXNMV, FMINNMV */ - case 0xf: /* FMAXV, FMINV */ - /* Bit 1 of size field encodes min vs max and the actual size - * depends on the encoding of the U bit. If not set (and FP16 - * enabled) then we do half-precision float instead of single - * precision. - */ - is_min =3D extract32(size, 1, 1); - if (!is_u && dc_isar_feature(aa64_fp16, s)) { - size =3D 1; - } else if (!is_u || !is_q || extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } else { - size =3D 2; - } - break; - default: - case 0x3: /* SADDLV, UADDLV */ - case 0xa: /* SMAXV, UMAXV */ - case 0x1a: /* SMINV, UMINV */ - case 0x1b: /* ADDV */ - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - elements =3D (is_q ? 16 : 8) >> size; - - { - /* Floating point vector reduction ops which work across 32 - * bit (single) or 16 bit (half-precision) intermediates. - * Note that correct NaN propagation requires that we do these - * operations in exactly the order specified by the pseudocode. - */ - TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 := FPST_FPCR); - int fpopcode =3D opcode | is_min << 4 | is_u << 5; - TCGv_i32 tcg_res =3D do_reduction_op(s, fpopcode, rn, size, - 0, elements, fpst); - write_fp_sreg(s, rd, tcg_res); - } -} - /* AdvSIMD modified immediate * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 = 0 * +---+---+----+---------------------+-----+-------+----+---+-------+----= --+ @@ -11735,7 +11666,6 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) static const AArch64DecodeTable data_proc_simd[] =3D { /* pattern , mask , fn */ { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, - { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede = it */ { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 5ab4b11781..c77f9fc987 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -54,11 +54,13 @@ @rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3D3 =20 @rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=3D1 esz= =3D0 +@rr_q1e2 ........ ........ ...... rn:5 rd:5 &qrr_e q=3D1 esz= =3D2 @r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=3D%rd q= =3D1 esz=3D0 @rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=3D1 esz= =3D0 @rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=3D1 esz= =3D3 @rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=3D1 esz= =3D3 =20 +@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=3D1 @qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e =20 @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=3D0 @@ -1166,3 +1168,15 @@ SMAXV 0.00 1110 .. 11000 01010 10 ..... ..= ... @qrr_e UMAXV 0.10 1110 .. 11000 01010 10 ..... ..... @qrr_e SMINV 0.00 1110 .. 11000 11010 10 ..... ..... @qrr_e UMINV 0.10 1110 .. 11000 11010 10 ..... ..... @qrr_e + +FMAXNMV_h 0.00 1110 00 11000 01100 10 ..... ..... @qrr_h +FMAXNMV_s 0110 1110 00 11000 01100 10 ..... ..... @rr_q1e2 + +FMINNMV_h 0.00 1110 10 11000 01100 10 ..... ..... @qrr_h +FMINNMV_s 0110 1110 10 11000 01100 10 ..... ..... @rr_q1e2 + +FMAXV_h 0.00 1110 00 11000 01111 10 ..... ..... @qrr_h +FMAXV_s 0110 1110 00 11000 01111 10 ..... ..... @rr_q1e2 + +FMINV_h 0.00 1110 10 11000 01111 10 ..... ..... @qrr_h +FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109101; cv=none; d=zohomail.com; s=zohoarc; b=FEGNr0vLVIK5HcYB9HqytHSThN/9xaOJuLQoqtDKEugY27sPSg1x4c4mLOAIiBBLiF5dEqznx5hDxOD7m2ncqyGk3XlIPh5R3NaVPApPv1rfsueylw0558T+huypPqHBGfWhBXpF/o6p6baqecXIA52JL7pAzHvxXp0Q8DUuw0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109101; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yy21jKPf3BqO69GaSde9b1IniNH9kQ/Ki9NWW9VeFKU=; b=gH7pz9xuwjH7zNX334lD2jYboko3s0o//fDOri3vUjDXcM3gkKp0MfyI538euPiFqT53jplelqFAre/7Fu0qKrbi2ebT6Eb1RYYnoFPkiO7UcCLU3a6EH17paSjIWGMcQw5oHx/k3cay35eetP+Lc4pwRRyQmTfOivGhz4X8MTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109101710192.66222302694086; Wed, 11 Sep 2024 19:45:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm2-00039n-1b; Wed, 11 Sep 2024 22:41:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlz-0002wI-54 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:31 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlw-0004Ar-Ob for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:30 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-207115e3056so4980215ad.2 for ; Wed, 11 Sep 2024 19:41:28 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109103354116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 74 ++++++++++++---------------------- target/arm/tcg/a64.decode | 4 ++ 2 files changed, 30 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index aec2f6a542..0e290062ef 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6888,6 +6888,31 @@ TRANS(FMINNMV_s, do_fp_reduction, a, gen_helper_vfp_= minnums) TRANS(FMAXV_s, do_fp_reduction, a, gen_helper_vfp_maxs) TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins) =20 +/* + * Floating-point Immediate + */ + +static bool trans_FMOVI_s(DisasContext *s, arg_FMOVI_s *a) +{ + switch (a->esz) { + case MO_32: + case MO_64: + break; + case MO_16: + if (!dc_isar_feature(aa64_fp16, s)) { + return false; + } + break; + default: + return false; + } + if (fp_access_check(s)) { + uint64_t imm =3D vfp_expand_imm(a->esz, a->imm); + write_fp_dreg(s, a->rd, tcg_constant_i64(imm)); + } + return true; +} + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -8625,53 +8650,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t = insn) } } =20 -/* Floating point immediate - * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 - * +---+---+---+-----------+------+---+------------+-------+------+------+ - * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | - * +---+---+---+-----------+------+---+------------+-------+------+------+ - */ -static void disas_fp_imm(DisasContext *s, uint32_t insn) -{ - int rd =3D extract32(insn, 0, 5); - int imm5 =3D extract32(insn, 5, 5); - int imm8 =3D extract32(insn, 13, 8); - int type =3D extract32(insn, 22, 2); - int mos =3D extract32(insn, 29, 3); - uint64_t imm; - MemOp sz; - - if (mos || imm5) { - unallocated_encoding(s); - return; - } - - switch (type) { - case 0: - sz =3D MO_32; - break; - case 1: - sz =3D MO_64; - break; - case 3: - sz =3D MO_16; - if (dc_isar_feature(aa64_fp16, s)) { - break; - } - /* fallthru */ - default: - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - imm =3D vfp_expand_imm(sz, imm8); - write_fp_dreg(s, rd, tcg_constant_i64(imm)); -} - /* Handle floating point <=3D> fixed point conversions. Note that we can * also deal with fp <=3D> integer conversions as a special case (scale = =3D=3D 64) * OPTME: consider handling that special case specially or at least skippi= ng @@ -9091,7 +9069,7 @@ static void disas_data_proc_fp(DisasContext *s, uint3= 2_t insn) switch (ctz32(extract32(insn, 12, 4))) { case 0: /* [15:12] =3D=3D xxx1 */ /* Floating point immediate */ - disas_fp_imm(s, insn); + unallocated_encoding(s); /* in decodetree */ break; case 1: /* [15:12] =3D=3D xx10 */ /* Floating point compare */ diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c77f9fc987..e11e293631 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1180,3 +1180,7 @@ FMAXV_s 0110 1110 00 11000 01111 10 ..... ...= .. @rr_q1e2 =20 FMINV_h 0.00 1110 10 11000 01111 10 ..... ..... @qrr_h FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2 + +# Floating-point Immediate + +FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=3D%esz_hsd --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109057; cv=none; d=zohomail.com; s=zohoarc; b=TcP4lACbY9EDwA9UfzKOIn3wFB5I3k6YC2rLVKtvc7yI/Je7qphWzglJMA4kYsHtkGpM2BZX2yssEm1vIgwfoSvp+Rs6iQM2ASWpjM7GyX/DvWxqX5VKRY0f6pZ0NkHkDCelh5DknQKCiWiiJBY5yNH0oZ1JYLL5sxCkLMFaIPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109057; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=I7s1BrHlJB9b3V3YlzUJL8l5KFCDRB+AiXZWrpR5UVc=; b=DmKXLx7QYcsSMAXq86CDQbOMA8v9irI53B2sF1jj1658Z1+WlkEntXzA0VJspXyDggIek/dL6UboXBIyodLseacVe7aQUXqS3qjEScGeUNskYnsXIP/DGg0RI3vp/TGx4BFy65BmJQ/KCAx47ZJjbncz8lbUNtHAUgYh3d8XCLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109057622835.3570407296598; Wed, 11 Sep 2024 19:44:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm7-0003WZ-EK; Wed, 11 Sep 2024 22:41:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZlz-00030I-UK for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:31 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZlx-0004BB-Mj for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:31 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2059112f0a7so4504875ad.3 for ; Wed, 11 Sep 2024 19:41:29 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108888; x=1726713688; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I7s1BrHlJB9b3V3YlzUJL8l5KFCDRB+AiXZWrpR5UVc=; b=h5VtzgMHk9lAVDEwDvYIMwJEy+pGin8KH34EWJItaZCHzIzXV5BQ2aNdBR1DgXvljW FBwgBlfJCBfOFAjkBoUbAFNDBdWtsHRzwFDlwCo0kKK3EAaUb/thVYG7QUc6uTRdZLJa +bq/oPCF6H79b+nZbemoY37Tarj0Om+pXG8twYz7M0mzwQA2FP3Xnqcunta0Tl/kEzuh 7xov5BjsiN96dLFOtG+2MAr9gNXXIfim80Q84/KWs+HIZNWNKI0ps2cHMl7nsK3Utfze uBs0+kFm98PBl/bImu3JOe3FUzTQwuYX84ayRAmXpW2GX+tj3JczGVGYwShDD317hH/s Qgng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108888; x=1726713688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I7s1BrHlJB9b3V3YlzUJL8l5KFCDRB+AiXZWrpR5UVc=; b=buNqeE40VHRPt+HfMDJ2m5bAEjg0BGmB2lYot/gaw5o2zb8LVl1VoP1WYssQBKsLOV G6lo4Tk6YXiyeDjh8t/8ZsABIPytR4WjXJgQZ12jBSPh0QuKBtzydbEynSpo+AsBNzmU P/zApTx7vaDlDFy9VhnbWMsJhLTpwU/YBVMy0W6njELHwriEJlbuvCevvo9JU571WJBm u7ZTVMmLwc97630SNQsZ6SvgsKiZigsySbruboHAAcmgXGGMITwEiCKa8kb+O1RbOY0w FV2HFT2md3zBYwu7AYiOODEh5UZbvCCiiPLsNUSXTXdEWhiv1aF0DZc96JAKhuTVzGan seSg== X-Gm-Message-State: AOJu0YzGJJJ/RD3HSAsWSfr7S76PXWpkbo4TVp+u/SN9j1k8iYyoTDqr OY4pIUq1im3hNfm2WBua9aXbDnqa4W5gfEon+20+MOZKQoAIYRzwXgbAhIJy4a/3LTjvE3JqtLA h X-Google-Smtp-Source: AGHT+IHn1TNunI8vZT/ZnHtkUX9DMIcSPXzIAdTuRrheUN+r+Xrc743eGaQ0JZNp1kZ8xrZCcdT9rg== X-Received: by 2002:a17:903:11c6:b0:207:1825:c65e with SMTP id d9443c01a7336-2076e34d945mr17356275ad.18.1726108888181; Wed, 11 Sep 2024 19:41:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 13/29] target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to decodetree Date: Wed, 11 Sep 2024 19:40:58 -0700 Message-ID: <20240912024114.1097832-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109059233116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 117 ++++++++++++++------------------- target/arm/tcg/a64.decode | 9 +++ 2 files changed, 59 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0e290062ef..53022f4fc0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6913,6 +6913,52 @@ static bool trans_FMOVI_s(DisasContext *s, arg_FMOVI= _s *a) return true; } =20 +/* + * Advanced SIMD Modified Immediate + */ + +static bool trans_FMOVI_v_h(DisasContext *s, arg_FMOVI_v_h *a) +{ + if (!dc_isar_feature(aa64_fp16, s)) { + return false; + } + if (fp_access_check(s)) { + tcg_gen_gvec_dup_imm(MO_16, vec_full_reg_offset(s, a->rd), + a->q ? 16 : 8, vec_full_reg_size(s), + vfp_expand_imm(MO_16, a->abcdefgh)); + } + return true; +} + +static void gen_movi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); +} + +static bool trans_Vimm(DisasContext *s, arg_Vimm *a) +{ + GVecGen2iFn *fn; + + /* Handle decode of cmode/op here between ORR/BIC/MOVI */ + if ((a->cmode & 1) && a->cmode < 12) { + /* For op=3D1, the imm will be inverted, so BIC becomes AND. */ + fn =3D a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori; + } else { + /* There is one unallocated cmode/op combination in this space */ + if (a->cmode =3D=3D 15 && a->op =3D=3D 1 && a->q =3D=3D 0) { + return false; + } + fn =3D gen_movi; + } + + if (fp_access_check(s)) { + uint64_t imm =3D asimd_imm_const(a->abcdefgh, a->cmode, a->op); + gen_gvec_fn2i(s, a->q, a->rd, a->rd, imm, fn, MO_64); + } + return true; +} + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9092,69 +9138,6 @@ static void disas_data_proc_fp(DisasContext *s, uint= 32_t insn) } } =20 -/* AdvSIMD modified immediate - * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 = 0 - * +---+---+----+---------------------+-----+-------+----+---+-------+----= --+ - * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd= | - * +---+---+----+---------------------+-----+-------+----+---+-------+----= --+ - * - * There are a number of operations that can be carried out here: - * MOVI - move (shifted) imm into register - * MVNI - move inverted (shifted) imm into register - * ORR - bitwise OR of (shifted) imm with register - * BIC - bitwise clear of (shifted) imm with register - * With ARMv8.2 we also have: - * FMOV half-precision - */ -static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) -{ - int rd =3D extract32(insn, 0, 5); - int cmode =3D extract32(insn, 12, 4); - int o2 =3D extract32(insn, 11, 1); - uint64_t abcdefgh =3D extract32(insn, 5, 5) | (extract32(insn, 16, 3) = << 5); - bool is_neg =3D extract32(insn, 29, 1); - bool is_q =3D extract32(insn, 30, 1); - uint64_t imm =3D 0; - - if (o2) { - if (cmode !=3D 0xf || is_neg) { - unallocated_encoding(s); - return; - } - /* FMOV (vector, immediate) - half-precision */ - if (!dc_isar_feature(aa64_fp16, s)) { - unallocated_encoding(s); - return; - } - imm =3D vfp_expand_imm(MO_16, abcdefgh); - /* now duplicate across the lanes */ - imm =3D dup_const(MO_16, imm); - } else { - if (cmode =3D=3D 0xf && is_neg && !is_q) { - unallocated_encoding(s); - return; - } - imm =3D asimd_imm_const(abcdefgh, cmode, is_neg); - } - - if (!fp_access_check(s)) { - return; - } - - if (!((cmode & 0x9) =3D=3D 0x1 || (cmode & 0xd) =3D=3D 0x9)) { - /* MOVI or MVNI, with MVNI negation handled above. */ - tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 = : 8, - vec_full_reg_size(s), imm); - } else { - /* ORR or BIC, with BIC negation to AND handled above. */ - if (is_neg) { - gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64); - } else { - gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); - } - } -} - /* * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) * @@ -10635,8 +10618,10 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) bool is_u =3D extract32(insn, 29, 1); bool is_q =3D extract32(insn, 30, 1); =20 - /* data_proc_simd[] has sent immh =3D=3D 0 to disas_simd_mod_imm. */ - assert(immh !=3D 0); + if (immh =3D=3D 0) { + unallocated_encoding(s); + return; + } =20 switch (opcode) { case 0x08: /* SRI */ @@ -11644,8 +11629,6 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) static const AArch64DecodeTable data_proc_simd[] =3D { /* pattern , mask , fn */ { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, - /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede = it */ - { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e11e293631..278d7873c2 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1184,3 +1184,12 @@ FMINV_s 0110 1110 10 11000 01111 10 ..... ..= ... @rr_q1e2 # Floating-point Immediate =20 FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=3D%esz_hsd + +# Advanced SIMD Modified Immediate + +%abcdefgh 16:3 5:5 + +FMOVI_v_h 0 q:1 00 1111 00000 ... 1111 11 ..... rd:5 %abcdefgh + +# MOVI, MVNI, ORR, BIC, FMOV are all intermixed via cmode. +Vimm 0 q:1 op:1 0 1111 00000 ... cmode:4 01 ..... rd:5 %abcdefgh --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726108998; cv=none; d=zohomail.com; s=zohoarc; b=hOZXXeN8nYAuxL2yhwv9O6MHWRXGBeknK+Zm8B4ixrl2+GcJJtfrfxH2OEWTHlml3b8cHZAfxa43r1dn6O+Fnx8QEMq3cl/ABVxfkg7n/yRZwuyQiqXM7NU2m1W4+vmk93by5G+ymt5YOwPtMQGItAJfLAAVuyeuNSTx9a98mCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726108998; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rkXBvyX56rezRPuXpFz/dXJhKRh6RJ5INCTz9rG8X5g=; b=BZLndvKorjvzpb5IZNoznSkdDOKKOWWwpbVP4NWfYnIfqH5epKmmkoOIeq53MrlalREB3lCvSju7/eYnYDq7/ydWzCAuqlFmK4RR/ptXp40eT3qtbGZxeutpdK1ZagEi+hv4JLx65A75PwMYy5pk9C/i7N/NzOeWlvYh47GQP90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172610899847445.4373378115838; Wed, 11 Sep 2024 19:43:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZmM-0004UA-0I; Wed, 11 Sep 2024 22:41:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZm0-00034D-O8 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:32 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZly-0004BQ-T0 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:32 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-20573eb852aso10682475ad.1 for ; Wed, 11 Sep 2024 19:41:29 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108889; x=1726713689; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rkXBvyX56rezRPuXpFz/dXJhKRh6RJ5INCTz9rG8X5g=; b=oLRvMETTWwtlNINcQhlHpyv4q3mou9GAdIwtkI/4v1uEU+1RER6OiZJPa88dtkcbBi 4B2DNCJOOZ08NUchpDZYHPIugK+MHZU7UU2VRYf5mlMBR70e2fxjlWYIwPpRZSV4/eJN iJwddjt3fLH9Y7Fwsi00Sx6tnj8zCXiqqWuMUsQdu/4Swxhs0J6DGGzuKi/3LvFPG2eQ eOWQ7iljJMSzGlTNLOaCj/Khfl/cnSiUYHvudtEQSc4w0EEWeBYPFy5G4RH7yP2Qchcn +0TclVNAa7kkGwsje4w8XqQsjoRKfgF3l0Fllv8gN+VR1IuIhzJU7hN8ncU16cT9Caa7 jOWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108889; x=1726713689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rkXBvyX56rezRPuXpFz/dXJhKRh6RJ5INCTz9rG8X5g=; b=m+cvF2s6+jmljIgIJCwKL8p1Q/h79vz7zJSQJgujQFsTbmGRySnjqwad5mARk15weU mZ84vJPz9fQiTCzLjFkmRKuitDoInztYWO03000AJSN+4IAWMVLrvoorEveZQ+lLSnhh qSPXRPzxBqsSQBP4J8Y1CUwJ81Hp4jmddizqfPiJ738A11YjpR12SjiZlqCG+9MsZSdA ZqfyxntjHc1vlDBlJDFKDKYjoPbeQ/Y3np0bLsp+YWV4PSJapaVFnxqX7P13YHkiIujH 2JCJ38fxW6k7Grimf8cJSiP9hGWN4fAYraDoLvYtP+dqvVcOkxkquM3m6FZy6GewJsyn 41GQ== X-Gm-Message-State: AOJu0YyI17W6LYZlne1TAxOWtu93ZBHIqvWdiOZuo/HNhHYA7HRKML4c m/x7vb2UiKxQpGAxnDrqK4YltQbMAJjk7vgANYbvnxnEQfm9LepVaXPCAAC/KU8MkKxK6/mV5A1 L X-Google-Smtp-Source: AGHT+IFaqAms5mB9elwsp5gKAMYQloo4a2VMEMebJShquKkmHVCtG0Cjj++SjdRKjnjU/4I6TRUWKA== X-Received: by 2002:a17:903:1112:b0:206:9818:5431 with SMTP id d9443c01a7336-2076e5f7c1dmr17603545ad.20.1726108888950; Wed, 11 Sep 2024 19:41:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 14/29] target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr Date: Wed, 11 Sep 2024 19:40:59 -0700 Message-ID: <20240912024114.1097832-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108998864116600 Content-Type: text/plain; charset="utf-8" Handle the two special cases within these new functions instead of higher in the call stack. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 5 +++++ target/arm/tcg/gengvec.c | 19 +++++++++++++++++++ target/arm/tcg/translate-a64.c | 16 +--------------- target/arm/tcg/translate-neon.c | 25 ++----------------------- 4 files changed, 27 insertions(+), 38 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3f0e9ceaa3..45990ae292 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -514,6 +514,11 @@ void gen_sqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, T= CGv_i64 b); void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); =20 +void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, + int64_t shift, uint32_t opr_sz, uint32_t max_sz); +void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, + int64_t shift, uint32_t opr_sz, uint32_t max_sz); + void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index c5fc1b6cfb..33c5084ea6 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -88,6 +88,25 @@ GEN_CMP0(gen_gvec_cgt0, TCG_COND_GT) =20 #undef GEN_CMP0 =20 +void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, + int64_t shift, uint32_t opr_sz, uint32_t max_sz) +{ + /* Signed shift out of range results in all-sign-bits */ + shift =3D MIN(shift, (8 << vece) - 1); + tcg_gen_gvec_sari(vece, rd_ofs, rm_ofs, shift, opr_sz, max_sz); +} + +void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, + int64_t shift, uint32_t opr_sz, uint32_t max_sz) +{ + /* Unsigned shift out of range results in all-zero-bits */ + if (shift >=3D (8 << vece)) { + tcg_gen_gvec_dup_imm(vece, rd_ofs, opr_sz, max_sz, 0); + } else { + tcg_gen_gvec_shri(vece, rd_ofs, rm_ofs, shift, opr_sz, max_sz); + } +} + static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) { tcg_gen_vec_sar8i_i64(a, a, shift); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 53022f4fc0..032bd33650 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10452,21 +10452,7 @@ static void handle_vec_simd_shri(DisasContext *s, = bool is_q, bool is_u, break; =20 case 0x00: /* SSHR / USHR */ - if (is_u) { - if (shift =3D=3D 8 << size) { - /* Shift count the same size as element size produces zero= . */ - tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), - is_q ? 16 : 8, vec_full_reg_size(s), = 0); - return; - } - gvec_fn =3D tcg_gen_gvec_shri; - } else { - /* Shift count the same size as element size produces all sign= . */ - if (shift =3D=3D 8 << size) { - shift -=3D 1; - } - gvec_fn =3D tcg_gen_gvec_sari; - } + gvec_fn =3D is_u ? gen_gvec_ushr : gen_gvec_sshr; break; =20 case 0x04: /* SRSHR / URSHR (rounding) */ diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 13cd31aad4..a31a78c347 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -1099,29 +1099,8 @@ DO_2SH(VRSHR_S, gen_gvec_srshr) DO_2SH(VRSHR_U, gen_gvec_urshr) DO_2SH(VRSRA_S, gen_gvec_srsra) DO_2SH(VRSRA_U, gen_gvec_ursra) - -static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) -{ - /* Signed shift out of range results in all-sign-bits */ - a->shift =3D MIN(a->shift, (8 << a->size) - 1); - return do_vector_2sh(s, a, tcg_gen_gvec_sari); -} - -static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_of= s, - int64_t shift, uint32_t oprsz, uint32_t maxsz) -{ - tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); -} - -static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) -{ - /* Shift out of range is architecturally valid and results in zero. */ - if (a->shift >=3D (8 << a->size)) { - return do_vector_2sh(s, a, gen_zero_rd_2sh); - } else { - return do_vector_2sh(s, a, tcg_gen_gvec_shri); - } -} +DO_2SH(VSHR_S, gen_gvec_sshr) +DO_2SH(VSHR_U, gen_gvec_ushr) =20 static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, NeonGenTwo64OpEnvFn *fn) --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726108956; cv=none; d=zohomail.com; s=zohoarc; b=EPoLth6iz7/FU8TOC/31WMKgarMCEIg/rnIeH/UrmSFKq6rc0RFbaxI8955QHYCxYzOmx1CH0Qhz3Az2XxBxZGx1W4P3uSDargE9SYmyT8n9sXMoR6h+XwUDb2Sci8G9PJv0sZ141D/fXm8KwE+28cGX1dgjBXtIDM8eYMk2Y54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726108956; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rxtmNqmck/OIJOdLsPx3DowunmnWeT0vfej1ZczH/vo=; b=D6DfODbhrB1XcYn896ke+cmfivjgDefKml93XusQim7xUJZcDeXGyhVg/GCE1r0ap/nYbJVbwZbfS74IB+DwpIMY0wc0t+h/ADAs3fTIGQlKxnEnjOPkir7CfiZIIcZTo1SvePNVPUavO3o2wiNAdTuYldRFgCmBPym0ZGF3fPU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726108956499879.4638668709728; Wed, 11 Sep 2024 19:42:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZmD-00040l-IT; Wed, 11 Sep 2024 22:41:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZm0-00034H-P7 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:32 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZly-0004Bs-WF for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:32 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-207397d1000so12570275ad.0 for ; Wed, 11 Sep 2024 19:41:30 -0700 (PDT) Received: from stoup.. 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} =20 - void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) +void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) { TCGv_i64 t =3D tcg_temp_new_i64(); =20 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109057; cv=none; d=zohomail.com; s=zohoarc; b=m5Gle+FkAFhKqAE/iQ9cMCq/syas9t9GxDEgKgFIHGy/Vw7sXw7sO+Q0CR22p/XHkNGdNZl4aZdxfT/xo3hwMG0Vk4lrOc5PTw570nGH1MQaaJzdHUUe6YMGgi5UH2vcQZs2OMv8bl00xu12SmoRHyYpqkgyo8XeIYF7ULskWAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109057; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108891; x=1726713691; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DaMmQV0DItj/xJn2ESSKL4CE/7QS+SLFEQ94VIkslEw=; b=lL2yC71fWwD3qnBMR8uvr/9aRkWE0M3+qG0atQGh+OmKempzLHN2qzXeOc3OoS1ynZ xwJT8AbvtbvXD6TdVw+sszSu0jCwtcKnO/QR9y4aE3+f6FxuGXGF9bMqwGIKvFDn2vQ5 i/MjHQBKqdM2Zzu4vO+YCmeoOjy3J8yR4ac4zdhQy17MJ835ysdTQ9kFkyBDwIEfydaD EvgSV9+OsKLbT+C+sBgLm305udUYJpaZr5mBf1AgXVCl6vpdzcTe6CuYbBMZNDcbx45s Vt1r/aisOz9pAi6lUJs5bg5dtlm6rZIDlWGW0eyiEgnIVjnOLILd2FRch9KiwjyjXpo5 lEsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108891; x=1726713691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DaMmQV0DItj/xJn2ESSKL4CE/7QS+SLFEQ94VIkslEw=; b=KjjTaPitptgKscbYWO1gynpQDDNFRiX03uOKzYBRBMwtw12pRitwgHHFCmtlvQTwMM u+MDDAqSHAIdNTHea1SqX+qQlAPJJZoouVyAda11dHHI0ap4dqx4LhB3y+WpOlOH34Zn wrtW8ULHH688T4PrP5XyB1HkyhSOz812YUiIUqC7vAz0vkDyYi1Q9yYajFmWcdBEoe20 6FOhom2WQTzlu1ukq+yx42g98RuDLSpkw77mVE5SVir+lFjQzzul5Ycd21fKVF/8tvX0 G7VXJ2o6h76cjQYDFIW2Q2eJM/V8m7w52BkZTQzoMWSUIiZPfOci07BiWZmRh2A3tVbi ixtA== X-Gm-Message-State: AOJu0YyuriIvLcFjR6rDwo3MfR/xbd+6XGBpdE05sr9lKBSPuYvMJrX3 Dy59WK4uXTZuEqiB1H4nEKYuqRVdbEs9qMObiCBRL0McFCkw1Y45JHBigtAK6uEp9zHhX3q+AwW Z X-Google-Smtp-Source: AGHT+IEAc6AB36RK+XFgnKU8uIMCgAawgTouWbCPOGM3QwfFSVC9tWqoca9M5Lrq9EZL03qDJAPJwA== X-Received: by 2002:a17:903:2345:b0:205:76c1:3742 with SMTP id d9443c01a7336-2076e551052mr17353805ad.3.1726108890649; Wed, 11 Sep 2024 19:41:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 16/29] target/arm: Convert handle_vec_simd_shri to decodetree Date: Wed, 11 Sep 2024 19:41:01 -0700 Message-ID: <20240912024114.1097832-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109059258116600 Content-Type: text/plain; charset="utf-8" This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 86 +++++++++++----------------------- target/arm/tcg/a64.decode | 63 ++++++++++++++++++++++++- 2 files changed, 89 insertions(+), 60 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 032bd33650..5c76cdf101 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6959,6 +6959,28 @@ static bool trans_Vimm(DisasContext *s, arg_Vimm *a) return true; } =20 +/* + * Advanced SIMD Shift by Immediate + */ + +static bool do_vec_shift_imm(DisasContext *s, arg_qrri_e *a, GVecGen2iFn *= fn) +{ + if (fp_access_check(s)) { + gen_gvec_fn2i(s, a->q, a->rd, a->rn, a->imm, fn, a->esz); + } + return true; +} + +TRANS(SSHR_v, do_vec_shift_imm, a, gen_gvec_sshr) +TRANS(USHR_v, do_vec_shift_imm, a, gen_gvec_ushr) +TRANS(SSRA_v, do_vec_shift_imm, a, gen_gvec_ssra) +TRANS(USRA_v, do_vec_shift_imm, a, gen_gvec_usra) +TRANS(SRSHR_v, do_vec_shift_imm, a, gen_gvec_srshr) +TRANS(URSHR_v, do_vec_shift_imm, a, gen_gvec_urshr) +TRANS(SRSRA_v, do_vec_shift_imm, a, gen_gvec_srsra) +TRANS(URSRA_v, do_vec_shift_imm, a, gen_gvec_ursra) +TRANS(SRI_v, do_vec_shift_imm, a, gen_gvec_sri) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -10423,53 +10445,6 @@ static void disas_simd_scalar_two_reg_misc(DisasCo= ntext *s, uint32_t insn) } } =20 -/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ -static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, - int immh, int immb, int opcode, int rn, i= nt rd) -{ - int size =3D 32 - clz32(immh) - 1; - int immhb =3D immh << 3 | immb; - int shift =3D 2 * (8 << size) - immhb; - GVecGen2iFn *gvec_fn; - - if (extract32(immh, 3, 1) && !is_q) { - unallocated_encoding(s); - return; - } - tcg_debug_assert(size <=3D 3); - - if (!fp_access_check(s)) { - return; - } - - switch (opcode) { - case 0x02: /* SSRA / USRA (accumulate) */ - gvec_fn =3D is_u ? gen_gvec_usra : gen_gvec_ssra; - break; - - case 0x08: /* SRI */ - gvec_fn =3D gen_gvec_sri; - break; - - case 0x00: /* SSHR / USHR */ - gvec_fn =3D is_u ? gen_gvec_ushr : gen_gvec_sshr; - break; - - case 0x04: /* SRSHR / URSHR (rounding) */ - gvec_fn =3D is_u ? gen_gvec_urshr : gen_gvec_srshr; - break; - - case 0x06: /* SRSRA / URSRA (accum + rounding) */ - gvec_fn =3D is_u ? gen_gvec_ursra : gen_gvec_srsra; - break; - - default: - g_assert_not_reached(); - } - - gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size); -} - /* SHL/SLI - Vector shift left */ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, int immh, int immb, int opcode, int rn, i= nt rd) @@ -10610,18 +10585,6 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) } =20 switch (opcode) { - case 0x08: /* SRI */ - if (!is_u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x00: /* SSHR / USHR */ - case 0x02: /* SSRA / USRA (accumulate) */ - case 0x04: /* SRSHR / URSHR (rounding) */ - case 0x06: /* SRSRA / URSRA (accum + rounding) */ - handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); - break; case 0x0a: /* SHL / SLI */ handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); break; @@ -10660,6 +10623,11 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn,= rd); return; default: + case 0x00: /* SSHR / USHR */ + case 0x02: /* SSRA / USRA (accumulate) */ + case 0x04: /* SRSHR / URSHR (rounding) */ + case 0x06: /* SRSRA / URSRA (accum + rounding) */ + case 0x08: /* SRI */ unallocated_encoding(s); return; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 278d7873c2..74ba1fa07c 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -34,6 +34,7 @@ &rrx_e rd rn rm idx esz &rrrr_e rd rn rm ra esz &qrr_e q rd rn esz +&qrri_e q rd rn imm esz &qrrr_e q rd rn rm esz &qrrx_e q rd rn rm idx esz &qrrrr_e q rd rn rm ra esz @@ -1185,11 +1186,71 @@ FMINV_s 0110 1110 10 11000 01111 10 ..... .= .... @rr_q1e2 =20 FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=3D%esz_hsd =20 -# Advanced SIMD Modified Immediate +# Advanced SIMD Modified Immediate / Shift by Immediate =20 %abcdefgh 16:3 5:5 =20 +# Right shifts are encoded as N - shift, where N is the element size in bi= ts. +%neon_rshift_i6 16:6 !function=3Drsub_64 +%neon_rshift_i5 16:5 !function=3Drsub_32 +%neon_rshift_i4 16:4 !function=3Drsub_16 +%neon_rshift_i3 16:3 !function=3Drsub_8 + +@q_shri_b . q:1 .. ..... 0001 ... ..... . rn:5 rd:5 \ + &qrri_e esz=3D0 imm=3D%neon_rshift_i3 +@q_shri_h . q:1 .. ..... 001 .... ..... . rn:5 rd:5 \ + &qrri_e esz=3D1 imm=3D%neon_rshift_i4 +@q_shri_s . q:1 .. ..... 01 ..... ..... . rn:5 rd:5 \ + &qrri_e esz=3D2 imm=3D%neon_rshift_i5 +@q_shri_d . 1 .. ..... 1 ...... ..... . rn:5 rd:5 \ + &qrri_e esz=3D3 imm=3D%neon_rshift_i6 q=3D1 + FMOVI_v_h 0 q:1 00 1111 00000 ... 1111 11 ..... rd:5 %abcdefgh =20 # MOVI, MVNI, ORR, BIC, FMOV are all intermixed via cmode. Vimm 0 q:1 op:1 0 1111 00000 ... cmode:4 01 ..... rd:5 %abcdefgh + +SSHR_v 0.00 11110 .... ... 00000 1 ..... ..... @q_shri_b +SSHR_v 0.00 11110 .... ... 00000 1 ..... ..... @q_shri_h +SSHR_v 0.00 11110 .... ... 00000 1 ..... ..... @q_shri_s +SSHR_v 0.00 11110 .... ... 00000 1 ..... ..... @q_shri_d + +USHR_v 0.10 11110 .... ... 00000 1 ..... ..... @q_shri_b +USHR_v 0.10 11110 .... ... 00000 1 ..... ..... @q_shri_h +USHR_v 0.10 11110 .... ... 00000 1 ..... ..... @q_shri_s +USHR_v 0.10 11110 .... ... 00000 1 ..... ..... @q_shri_d + +SSRA_v 0.00 11110 .... ... 00010 1 ..... ..... @q_shri_b +SSRA_v 0.00 11110 .... ... 00010 1 ..... ..... @q_shri_h +SSRA_v 0.00 11110 .... ... 00010 1 ..... ..... @q_shri_s +SSRA_v 0.00 11110 .... ... 00010 1 ..... ..... @q_shri_d + +USRA_v 0.10 11110 .... ... 00010 1 ..... ..... @q_shri_b +USRA_v 0.10 11110 .... ... 00010 1 ..... ..... @q_shri_h +USRA_v 0.10 11110 .... ... 00010 1 ..... ..... @q_shri_s +USRA_v 0.10 11110 .... ... 00010 1 ..... ..... @q_shri_d + +SRSHR_v 0.00 11110 .... ... 00100 1 ..... ..... @q_shri_b +SRSHR_v 0.00 11110 .... ... 00100 1 ..... ..... @q_shri_h +SRSHR_v 0.00 11110 .... ... 00100 1 ..... ..... @q_shri_s +SRSHR_v 0.00 11110 .... ... 00100 1 ..... ..... @q_shri_d + +URSHR_v 0.10 11110 .... ... 00100 1 ..... ..... @q_shri_b +URSHR_v 0.10 11110 .... ... 00100 1 ..... ..... @q_shri_h +URSHR_v 0.10 11110 .... ... 00100 1 ..... ..... @q_shri_s +URSHR_v 0.10 11110 .... ... 00100 1 ..... ..... @q_shri_d + +SRSRA_v 0.00 11110 .... ... 00110 1 ..... ..... @q_shri_b +SRSRA_v 0.00 11110 .... ... 00110 1 ..... ..... @q_shri_h +SRSRA_v 0.00 11110 .... ... 00110 1 ..... ..... @q_shri_s +SRSRA_v 0.00 11110 .... ... 00110 1 ..... ..... @q_shri_d + +URSRA_v 0.10 11110 .... ... 00110 1 ..... ..... @q_shri_b +URSRA_v 0.10 11110 .... ... 00110 1 ..... ..... @q_shri_h +URSRA_v 0.10 11110 .... ... 00110 1 ..... ..... @q_shri_s +URSRA_v 0.10 11110 .... ... 00110 1 ..... ..... @q_shri_d + +SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_b +SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_h +SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_s +SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_d --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726108958; cv=none; d=zohomail.com; s=zohoarc; b=ZTY/5eZn9EYfcMsXTMNggFn4/n/JvPVN5C/onYzvV1Xlsw6bnjvw2iqcdBKEFBAY3lT08bZaQZIvFXioRK8RjLv4SkXXFdDa3lsp56zhFI3Otk9R7EVh5ecjkadsiZVKQg4PdNSfRnTm1ZGSM11yqjoFwYbBfsLRSXoYXAVtYxI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726108958; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zRNfpJRjZxrz6sJrwEuh2h0rfe1pxZcw68KhhXlHk4Q=; b=Gyrsw4x7ArkMXgP9HEv0HIouw/CKl+/TbZTlqnGu7EZVvy53WBsAFOCBAC8vcVSOJpu+BGw8+WFNKRNMjz1Soie3ES+vS5SntR8Ry98mErY+ASPsu9X+cdbQLInOJ4AKnrVun5ZDj7DBkiE1z2UBtoBbV2fOPl6ib19EFoE2ldc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726108958727209.14310336315089; Wed, 11 Sep 2024 19:42:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZm9-0003ir-IS; Wed, 11 Sep 2024 22:41:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZm2-0003DM-ST for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:35 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZm0-0004Cn-WD for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:34 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-201d5af11a4so5817935ad.3 for ; Wed, 11 Sep 2024 19:41:32 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108892; x=1726713692; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zRNfpJRjZxrz6sJrwEuh2h0rfe1pxZcw68KhhXlHk4Q=; b=t78a3QH4v26VcVyPlbpowVJBCxHVMm1rKItqLPooFbZYewE7eEHINKDkELieaxzprw 8AIGGZ5NEtKKco9WGvfC2ntVsi0mmSBiOdQZmiOWkgYYMo3UpPYErI0c30nN4OmfLNzm PtIsqFRGim22wgtew0WzFmLy8gRtIzoMVAKeGoWWg3cXRFuzE3ehWwj6Xq5+PCvkT2zO 7ZJyCaeDF17Y0/+5REVd4h+QG49UVVCN/MQUx8ZheYl6yuY2DRlCMzGlNZNJmCBFeQ7M xuYm8F6pigDNcCsBOXh+hP5V9Xo7OQ14ZLV/VIIU1Jodw/qbCcwVQilwcFpYu3iASBy4 OI/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108892; x=1726713692; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zRNfpJRjZxrz6sJrwEuh2h0rfe1pxZcw68KhhXlHk4Q=; b=jITpwitHCo4RohkhD+UB7i94GTLAEyZVnRiA3t6dzvzjNr7AVJ2jnSSHN6krO3p553 hQ5byIHApD39ax/Hc0dmyUJYUMYLErSRkIGK7JxAkOBktDfWTM/ShyiH5vtMFr4Z7fbw EVrE5SBdrldM0d5b2uL5/AgxVwbKO6/DZ7//G77SovJ0ogcyKFf9b+NW7VCaOkEAaX7Y LWRKy7CjI26DpVRKWpbSqWqxWZ87YBZU/SBSyl6vpw7Qv49QZQ65RXyoL4wjZSu8Tt03 o2MFWXipPUskw7S3nnodSlUZhmsxIwtfGWUpb4i8fU7GovuAi9bUC3eDnDLNmpJ8jzoe Nk6g== X-Gm-Message-State: AOJu0YxWtopbM48GZVvUOadIOx5nTXs5D3s9QHr26poDxO1mtUz7exJ3 JLCMiB6MTi8WUG06VzHI9vxu2kQiX5JN3Cvof2n4uunMnZBJe2dX9KOggdR4Ynjtg1zxx4GmpSP U X-Google-Smtp-Source: AGHT+IHI4uzaQFAjMd9mf0HYMraNF7NCohwlv2/9plc3ZoTwmDIoEQCu76B4FMb5bWUQB3vixPXbKg== X-Received: by 2002:a17:902:da8c:b0:206:fd9d:b88d with SMTP id d9443c01a7336-2076e44def0mr17935605ad.61.1726108891645; Wed, 11 Sep 2024 19:41:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 17/29] target/arm: Convert handle_vec_simd_shli to decodetree Date: Wed, 11 Sep 2024 19:41:02 -0700 Message-ID: <20240912024114.1097832-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108960753116600 Content-Type: text/plain; charset="utf-8" This includes SHL and SLI. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 33 +++------------------------------ target/arm/tcg/a64.decode | 15 +++++++++++++++ 2 files changed, 18 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5c76cdf101..1225aac665 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6980,6 +6980,8 @@ TRANS(URSHR_v, do_vec_shift_imm, a, gen_gvec_urshr) TRANS(SRSRA_v, do_vec_shift_imm, a, gen_gvec_srsra) TRANS(URSRA_v, do_vec_shift_imm, a, gen_gvec_ursra) TRANS(SRI_v, do_vec_shift_imm, a, gen_gvec_sri) +TRANS(SHL_v, do_vec_shift_imm, a, tcg_gen_gvec_shli) +TRANS(SLI_v, do_vec_shift_imm, a, gen_gvec_sli); =20 /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the @@ -10445,33 +10447,6 @@ static void disas_simd_scalar_two_reg_misc(DisasCo= ntext *s, uint32_t insn) } } =20 -/* SHL/SLI - Vector shift left */ -static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, - int immh, int immb, int opcode, int rn, i= nt rd) -{ - int size =3D 32 - clz32(immh) - 1; - int immhb =3D immh << 3 | immb; - int shift =3D immhb - (8 << size); - - /* Range of size is limited by decode: immh is a non-zero 4 bit field = */ - assert(size >=3D 0 && size <=3D 3); - - if (extract32(immh, 3, 1) && !is_q) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - if (insert) { - gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sli, size); - } else { - gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); - } -} - /* USHLL/SHLL - Vector shift left with widening */ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, int immh, int immb, int opcode, int rn, i= nt rd) @@ -10585,9 +10560,6 @@ static void disas_simd_shift_imm(DisasContext *s, u= int32_t insn) } =20 switch (opcode) { - case 0x0a: /* SHL / SLI */ - handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); - break; case 0x10: /* SHRN */ case 0x11: /* RSHRN / SQRSHRUN */ if (is_u) { @@ -10628,6 +10600,7 @@ static void disas_simd_shift_imm(DisasContext *s, u= int32_t insn) case 0x04: /* SRSHR / URSHR (rounding) */ case 0x06: /* SRSRA / URSRA (accum + rounding) */ case 0x08: /* SRI */ + case 0x0a: /* SHL / SLI */ unallocated_encoding(s); return; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 74ba1fa07c..77b860a3f2 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1205,6 +1205,11 @@ FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 = esz=3D%esz_hsd @q_shri_d . 1 .. ..... 1 ...... ..... . rn:5 rd:5 \ &qrri_e esz=3D3 imm=3D%neon_rshift_i6 q=3D1 =20 +@q_shli_b . q:1 .. ..... 0001 imm:3 ..... . rn:5 rd:5 &qrri_e esz=3D0 +@q_shli_h . q:1 .. ..... 001 imm:4 ..... . rn:5 rd:5 &qrri_e esz=3D1 +@q_shli_s . q:1 .. ..... 01 imm:5 ..... . rn:5 rd:5 &qrri_e esz=3D2 +@q_shli_d . 1 .. ..... 1 imm:6 ..... . rn:5 rd:5 &qrri_e esz=3D= 3 q=3D1 + FMOVI_v_h 0 q:1 00 1111 00000 ... 1111 11 ..... rd:5 %abcdefgh =20 # MOVI, MVNI, ORR, BIC, FMOV are all intermixed via cmode. @@ -1254,3 +1259,13 @@ SRI_v 0.10 11110 .... ... 01000 1 ..... ..= ... @q_shri_b SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_h SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_s SRI_v 0.10 11110 .... ... 01000 1 ..... ..... @q_shri_d + +SHL_v 0.00 11110 .... ... 01010 1 ..... ..... @q_shli_b +SHL_v 0.00 11110 .... ... 01010 1 ..... ..... @q_shli_h +SHL_v 0.00 11110 .... ... 01010 1 ..... ..... @q_shli_s +SHL_v 0.00 11110 .... ... 01010 1 ..... ..... @q_shli_d + +SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_b +SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_h +SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_s +SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_d --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108892; x=1726713692; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YSOEdaLeZCfPJbRKNmK3UxW2mNrgDyxy1eu96FTDCng=; b=qIjz3EFeOJleaipmATgNyYxcU5wx6Ce3hm5OoAyc/2TeWM80E536nH2il1I0XiQgpu EOQBbhvs7MnUmH5fOkEVg0JXmXaOpkYvF9soavuZJwLC0rCv3BKhW43tMIV3rQDgoJop MDt/sGmOows6SblQ4puKSbJB1g9C1JNTW2yz465E9fMVlthekEwCXjjaoP88E/DofBAm 8vc5++Rq8fqqoiY7/7TLG01O436vBXK1Czur3y2jmdRoGynlSJJvaRn3tS7jTcBJvMUS 8Bq8iKFCXvgqKDoVu2zCZbw2O/JG6kQYnTvkWH3wtbxpmQSRm3fSdyZaInZP2z+6mhb2 e2hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108892; x=1726713692; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YSOEdaLeZCfPJbRKNmK3UxW2mNrgDyxy1eu96FTDCng=; b=fySgnnPLyD2SDps76JLJCjIs8zYsO3RuS6ihgWNulZn0w7tLy6e4h2DMdXSfRiBABM /7Y/b7IdZv7TRDqxEHUs0tFa2lp/gQJQaGuzwFoP63kvM3D5vv9f+AUUJzXZq8dGSE7j QQ+O56wh8TrtLKzWOGoAO+tW/tiEt7BpTi14BbHpjI2v9ezK+TiBjWnHreUAbfZX0+iX 7SIrZ7VkQ1VIe8DR3VUQzdSZYpPkKXanIsaYMxx2CH8sLyS0lfShqIOAlgM5GlbdUjIs yGt5unuLE8jgfzCN6sKNW8+QpMPF2MlGZFt65TqbbUKn2PqbjMSIeMtRtS5/wK421Kml 8HmQ== X-Gm-Message-State: AOJu0YykSr4oDTm+xuxO9WoN0AjDzYS1VxFQ0kyuG+FPQzFGiE/0X6Yz 5ovhFL/JU7iOB5HNTr8Ahw2QMN9X8XKXyWB//pRENzNfC8k+pOWnptZbvBfIl/GZvxgfN6muxeL m X-Google-Smtp-Source: AGHT+IH76nIjQ8WUnq02DrrnNsIW5kh1dzXt5iTLq2bBCGUbNHqZdh7YRO2BoWy7FkjiXEV0gRybig== X-Received: by 2002:a17:902:d4ce:b0:1fd:96c7:24f5 with SMTP id d9443c01a7336-2074c5d2351mr91016755ad.5.1726108892444; Wed, 11 Sep 2024 19:41:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 18/29] target/arm: Use {, s}extract in handle_vec_simd_wshli Date: Wed, 11 Sep 2024 19:41:03 -0700 Message-ID: <20240912024114.1097832-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1726109209739116600 Content-Type: text/plain; charset="utf-8" Combine the right shift with the extension via the tcg extract operations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1225aac665..740620074a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10477,8 +10477,11 @@ static void handle_vec_simd_wshli(DisasContext *s,= bool is_q, bool is_u, read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); =20 for (i =3D 0; i < elements; i++) { - tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); - ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); + if (is_u) { + tcg_gen_extract_i64(tcg_rd, tcg_rn, i * esize, esize); + } else { + tcg_gen_sextract_i64(tcg_rd, tcg_rn, i * esize, esize); + } tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); write_vec_element(s, tcg_rd, rd, i, size + 1); } --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726108974; cv=none; d=zohomail.com; s=zohoarc; b=B7Dqy20pNozvM/60i7M0gQudjtEArIAYF9h4vx4godj0zsFMJ4gfXSWjsQ+kzgNUspuncs39KtSQs0ivEEwgOWdB/02i0qVLUXMkChyhHX1fBcsmOVA5SreZjfzQoQo1D13/ThjsjuugVIyay+TbwPRsyffSwjcxHz/lQDPF8q8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726108974; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vnCv64h+Jeh9/RoiV0zaMJCTxvJV9tTWODBEEi7v64Q=; b=oAWN+UyQGon9H5Z6gKuBKgVoXEkaLflPMtCPV2DIiPL7V/F+JXktpp4aktv5xayyMjj+Zyfkqd7Z0ZOrv2ovttVgn933SzMoUlQONm2Ld9Ytkd30i7TxXeUz17waYv45DJr2BdyF6x38LON2rOnvoYoyxBqJy7YN0YFSIRrFKrM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726108974753517.1297295959846; Wed, 11 Sep 2024 19:42:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZmB-0003m3-4a; Wed, 11 Sep 2024 22:41:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZm4-0003L1-LT for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:36 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZm2-0004DV-Su for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:36 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-20570b42f24so5562625ad.1 for ; Wed, 11 Sep 2024 19:41:34 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108976834116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 81 ++++++++++++++++------------------ target/arm/tcg/a64.decode | 8 ++++ 2 files changed, 45 insertions(+), 44 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 740620074a..e00d7fbf48 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6983,6 +6983,42 @@ TRANS(SRI_v, do_vec_shift_imm, a, gen_gvec_sri) TRANS(SHL_v, do_vec_shift_imm, a, tcg_gen_gvec_shli) TRANS(SLI_v, do_vec_shift_imm, a, gen_gvec_sli); =20 +static bool do_vec_shift_imm_wide(DisasContext *s, arg_qrri_e *a, bool is_= u) +{ + TCGv_i64 tcg_rn, tcg_rd; + int esz =3D a->esz; + int esize; + + if (!fp_access_check(s)) { + return true; + } + + /* + * For the LL variants the store is larger than the load, + * so if rd =3D=3D rn we would overwrite parts of our input. + * So load everything right now and use shifts in the main loop. + */ + tcg_rd =3D tcg_temp_new_i64(); + tcg_rn =3D tcg_temp_new_i64(); + read_vec_element(s, tcg_rn, a->rn, a->q, MO_64); + + esize =3D 8 << esz; + for (int i =3D 0, elements =3D 8 >> esz; i < elements; i++) { + if (is_u) { + tcg_gen_extract_i64(tcg_rd, tcg_rn, i * esize, esize); + } else { + tcg_gen_sextract_i64(tcg_rd, tcg_rn, i * esize, esize); + } + tcg_gen_shli_i64(tcg_rd, tcg_rd, a->imm); + write_vec_element(s, tcg_rd, a->rd, i, esz + 1); + } + clear_vec_high(s, true, a->rd); + return true; +} + +TRANS(SSHLL_v, do_vec_shift_imm_wide, a, false) +TRANS(USHLL_v, do_vec_shift_imm_wide, a, true) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -10447,47 +10483,6 @@ static void disas_simd_scalar_two_reg_misc(DisasCo= ntext *s, uint32_t insn) } } =20 -/* USHLL/SHLL - Vector shift left with widening */ -static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, - int immh, int immb, int opcode, int rn, i= nt rd) -{ - int size =3D 32 - clz32(immh) - 1; - int immhb =3D immh << 3 | immb; - int shift =3D immhb - (8 << size); - int dsize =3D 64; - int esize =3D 8 << size; - int elements =3D dsize/esize; - TCGv_i64 tcg_rn =3D tcg_temp_new_i64(); - TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); - int i; - - if (size >=3D 3) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - /* For the LL variants the store is larger than the load, - * so if rd =3D=3D rn we would overwrite parts of our input. - * So load everything right now and use shifts in the main loop. - */ - read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); - - for (i =3D 0; i < elements; i++) { - if (is_u) { - tcg_gen_extract_i64(tcg_rd, tcg_rn, i * esize, esize); - } else { - tcg_gen_sextract_i64(tcg_rd, tcg_rn, i * esize, esize); - } - tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); - write_vec_element(s, tcg_rd, rd, i, size + 1); - } - clear_vec_high(s, true, rd); -} - /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ static void handle_vec_simd_shrn(DisasContext *s, bool is_q, int immh, int immb, int opcode, int rn, i= nt rd) @@ -10577,9 +10572,6 @@ static void disas_simd_shift_imm(DisasContext *s, u= int32_t insn) handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, opcode, rn, rd); break; - case 0x14: /* SSHLL / USHLL */ - handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); - break; case 0x1c: /* SCVTF / UCVTF */ handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, opcode, rn, rd); @@ -10604,6 +10596,7 @@ static void disas_simd_shift_imm(DisasContext *s, u= int32_t insn) case 0x06: /* SRSRA / URSRA (accum + rounding) */ case 0x08: /* SRI */ case 0x0a: /* SHL / SLI */ + case 0x14: /* SSHLL / USHLL */ unallocated_encoding(s); return; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 77b860a3f2..bf67f8a357 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1269,3 +1269,11 @@ SLI_v 0.10 11110 .... ... 01010 1 ..... ..= ... @q_shli_b SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_h SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_s SLI_v 0.10 11110 .... ... 01010 1 ..... ..... @q_shli_d + +SSHLL_v 0.00 11110 .... ... 10100 1 ..... ..... @q_shli_b +SSHLL_v 0.00 11110 .... ... 10100 1 ..... ..... @q_shli_h +SSHLL_v 0.00 11110 .... ... 10100 1 ..... ..... @q_shli_s + +USHLL_v 0.10 11110 .... ... 10100 1 ..... ..... @q_shli_b +USHLL_v 0.10 11110 .... ... 10100 1 ..... ..... @q_shli_h +USHLL_v 0.10 11110 .... ... 10100 1 ..... ..... @q_shli_s --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108894; x=1726713694; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Si86JKCuT9dzTb6LuA2zkdzwmeHcws3bbEbFgiDwDVI=; b=SsnD3XWfxPEayb/GB5zK+dBZuvJIzld1xWILRtrkKHBQOezIbBj6nVrJgeS6YXqEFE CPPYluqZG2/mKyEIQqQqNEPwam6hco1NlY31f7VLkqEqS0830YWoaIu3fOxYfcHzWls2 HrRhOnNslTFS5fBCseojNgZHBUBunKNTVGLwsbfK0kiJ+7rxTfRy7i8T3hc5FGV4hs0p 1pdJ58YOjhTh7O7sKeHomde0GMl40b0aWyjE5abolNV84G11RqYicqtdl3D45XEAJ/V2 E7eNztenuEaq0ZY8TPZZ+vlix07fowtetgU4EQQYBkQI9wOgg1TBBts+q4lfJurssINq 4rfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108894; x=1726713694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Si86JKCuT9dzTb6LuA2zkdzwmeHcws3bbEbFgiDwDVI=; b=VutMAuMxL2LFc0v7b/H/kAsfGko9+H5DRhzl+x33VNT7Iost6WPTZiITAYujRPsnLC UYPl8sYu+RxzdrsRs1aIH/YzqVIHesbAxPfupr5SNZKqxQXuPDMOJqH/NvyWTAEarn0b dYRRGcDZAZr+WEaBlu0cr/LmX5bE7fmiWI38WbLDz6KVsf9mx0KhqT0QWdsiIzf7ZfRE VMCG0a6IXpL9CG19FOZfsW5ZsoC/KREA7XKRx4Veo8ac/F37isRvKwhRqvGhbKsq8Rj/ USF4ypz0pN92e/ZErZfj+hFKNYTqyCWWqR/Sp4ZwVhzv5mZkQUmT3eXx0FCLoqP1vhrA 6Bmw== X-Gm-Message-State: AOJu0YwVhXUiGIT+4uOeD1dTLzIOvKMpjJZ+aP173xPS0FH6g0TMbAgK VoM59DkJPijVLlAFYUASTDiKuM0U/ICyhNNmGD8yK7SYOrCBMjA+n8YpjOV8uzqNl1vOd/ABZOz 6 X-Google-Smtp-Source: AGHT+IF31ZuNxpMn7jNtA0K+vGb4y6JSvHCaX/gtiyXmo1x1vSK1liCeM12DdQQz8ad/9DJ5MGzPlg== X-Received: by 2002:a17:903:41c3:b0:207:1de9:1014 with SMTP id d9443c01a7336-2076e38f304mr23558695ad.34.1726108894313; Wed, 11 Sep 2024 19:41:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 20/29] target/arm: Push tcg_rnd into handle_shri_with_rndacc Date: Wed, 11 Sep 2024 19:41:05 -0700 Message-ID: <20240912024114.1097832-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726108994966116600 We always pass the same value for round; compute it within common code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 32 ++++++-------------------------- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e00d7fbf48..e59236330a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -9205,11 +9205,10 @@ static void disas_data_proc_fp(DisasContext *s, uin= t32_t insn) * the vector and scalar code. */ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, - TCGv_i64 tcg_rnd, bool accumulate, + bool round, bool accumulate, bool is_u, int size, int shift) { bool extended_result =3D false; - bool round =3D tcg_rnd !=3D NULL; int ext_lshift =3D 0; TCGv_i64 tcg_src_hi; =20 @@ -9227,6 +9226,7 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res,= TCGv_i64 tcg_src, =20 /* Deal with the rounding step */ if (round) { + TCGv_i64 tcg_rnd =3D tcg_constant_i64(1ull << (shift - 1)); if (extended_result) { TCGv_i64 tcg_zero =3D tcg_constant_i64(0); if (!is_u) { @@ -9294,7 +9294,6 @@ static void handle_scalar_simd_shri(DisasContext *s, bool insert =3D false; TCGv_i64 tcg_rn; TCGv_i64 tcg_rd; - TCGv_i64 tcg_round; =20 if (!extract32(immh, 3, 1)) { unallocated_encoding(s); @@ -9320,12 +9319,6 @@ static void handle_scalar_simd_shri(DisasContext *s, break; } =20 - if (round) { - tcg_round =3D tcg_constant_i64(1ULL << (shift - 1)); - } else { - tcg_round =3D NULL; - } - tcg_rn =3D read_fp_dreg(s, rn); tcg_rd =3D (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new= _i64(); =20 @@ -9339,7 +9332,7 @@ static void handle_scalar_simd_shri(DisasContext *s, tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); } } else { - handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + handle_shri_with_rndacc(tcg_rd, tcg_rn, round, accumulate, is_u, size, shift); } =20 @@ -9392,7 +9385,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, int elements =3D is_scalar ? 1 : (64 / esize); bool round =3D extract32(opcode, 0, 1); MemOp ldop =3D (size + 1) | (is_u_shift ? 0 : MO_SIGN); - TCGv_i64 tcg_rn, tcg_rd, tcg_round; + TCGv_i64 tcg_rn, tcg_rd; TCGv_i32 tcg_rd_narrowed; TCGv_i64 tcg_final; =20 @@ -9437,15 +9430,9 @@ static void handle_vec_simd_sqshrn(DisasContext *s, = bool is_scalar, bool is_q, tcg_rd_narrowed =3D tcg_temp_new_i32(); tcg_final =3D tcg_temp_new_i64(); =20 - if (round) { - tcg_round =3D tcg_constant_i64(1ULL << (shift - 1)); - } else { - tcg_round =3D NULL; - } - for (i =3D 0; i < elements; i++) { read_vec_element(s, tcg_rn, rn, i, ldop); - handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + handle_shri_with_rndacc(tcg_rd, tcg_rn, round, false, is_u_shift, size+1, shift); narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd); tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); @@ -10495,7 +10482,6 @@ static void handle_vec_simd_shrn(DisasContext *s, b= ool is_q, int shift =3D (2 * esize) - immhb; bool round =3D extract32(opcode, 0, 1); TCGv_i64 tcg_rn, tcg_rd, tcg_final; - TCGv_i64 tcg_round; int i; =20 if (extract32(immh, 3, 1)) { @@ -10512,15 +10498,9 @@ static void handle_vec_simd_shrn(DisasContext *s, = bool is_q, tcg_final =3D tcg_temp_new_i64(); read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); =20 - if (round) { - tcg_round =3D tcg_constant_i64(1ULL << (shift - 1)); - } else { - tcg_round =3D NULL; - } - for (i =3D 0; i < elements; i++) { read_vec_element(s, tcg_rn, rn, i, size+1); - handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, + handle_shri_with_rndacc(tcg_rd, tcg_rn, round, false, true, size+1, shift); =20 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize= ); --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109009; cv=none; d=zohomail.com; s=zohoarc; b=bOS4li9VpIiMSCo3vXer+6IsYPpn+vX9e1aOBBs50LyfcC3acLqjnr+AOp+Eeli6MgeKHl7Tf8GBnaIPzjUAkSJg4QHw0BiwNxnKhN6VKCLNOW1BC4rZDl0cAV0BmbuZjPisIPYAWjD0aTQB7K+v2tZgXZnALrGOX07jDjyDkMM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109009; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HEdXGjZiuvLSMMB79GQjRx+E1UF3hWAu/88yWPAgnX4=; b=e1VRSbrwk8iHXNAQTd+u/F90AC8fI4t0TUDAPCABMcPp6hd0n8iHw8Gm0jFOHRzQSEu+MtZQzhCUafw+w2kDqVV/SSsZc8A8nTWU9OY1gguwI12Zo6+GEyT3wq0gu6R+CIhF9NJXcLZ1Cm8D1373Tlea9jrNI20q2QigUHsH5/A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109009027271.31678801085934; Wed, 11 Sep 2024 19:43:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZmn-0006q5-Uf; Wed, 11 Sep 2024 22:42:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZm6-0003Tc-LO for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:38 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZm4-0004EO-S7 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:38 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2057c6c57b5so2197325ad.1 for ; Wed, 11 Sep 2024 19:41:36 -0700 (PDT) Received: from stoup.. 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108895; x=1726713695; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HEdXGjZiuvLSMMB79GQjRx+E1UF3hWAu/88yWPAgnX4=; b=IU5HnVY8gz8O07fFiUUZNr2st0Vd2M4g3dxHUScCrMNyGN4I8pBDzBLdhAGZ7E7OWi nobRWetGpfVY+waC8J/4L5TnYuMw/bTHJdRz9mXiIzH7nmRjqQR8/7X2gqmWzQekdaEf kz0yQA/tBDX3EDjEssNVWxcgDNjj3oPE+0JDVXGlXhA5TcRsxB3TdweofjGYvR2mSFzE e8Igc7u5fJ4jZcdzGLFP3XPW+qoO6Nm/E8J2mKGd5qqSdfmrRjtclmSSMQM6fD3cDNEI oWmejr0sh1ot71DsQyKkj2u2Gm/xaCupblsfvNzHCtnQUaniZdZ/gnf3rjUNxATbUG4S Ky8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108895; x=1726713695; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HEdXGjZiuvLSMMB79GQjRx+E1UF3hWAu/88yWPAgnX4=; b=lctswCjcHDuOpVbl8EtbQG8zS5g+ps4v6jl5RyzOkWWLN/AWEhgrnbuz0XzzLhvP81 iozz50uf++4qBog0CHz8AsvLX8/j9K6TnhLFHLp2MkcUN6aicfgFQaenj70wyWlBBlHT SmgBXdBq2pqHz/Opya+NobLLVn8Ru3jb4t1BJG6gIuuvMGHuWPNYvbDlmU5NVEsMa3uO qH54NBOde2CNcXzPxbpMdfp/z5DkdtjDZTMVHk4TChGi/1IanXZvS+67mz6f6+rIcHUW w0AuAF1FMnWOW3xkjeFkZn+ssVi5OWZJn2MUmAl/b3KL2VmAAnJDOl5GC57ebOGlsu2w GDDA== X-Gm-Message-State: AOJu0Ywmr8ORdplTrXirw3EIyfdaI90W38Ocnret1o/nTAd748kS5mjW hXGaw+svvO1XnJfUsoxWvQZ84SSoM6i5voZ/FCjVTEtlHDvgHORnhFkOuVfHROAz23B9TBMLmDG 3 X-Google-Smtp-Source: AGHT+IFWlrqqFddOr+RL4QumS1C1E0vbTPZtHum1AV1JEMHXGYGtEsZcWxHmLTqKTKsFx2myi7SmoQ== X-Received: by 2002:a17:902:f542:b0:206:9dfb:3e9e with SMTP id d9443c01a7336-2074c5eebbdmr88266375ad.10.1726108895355; Wed, 11 Sep 2024 19:41:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 21/29] target/arm: Split out subroutines of handle_shri_with_rndacc Date: Wed, 11 Sep 2024 19:41:06 -0700 Message-ID: <20240912024114.1097832-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109011040116600 Content-Type: text/plain; charset="utf-8" There isn't a lot of commonality along the different paths of handle_shri_with_rndacc. Split them out to separate functions, which will be usable during the decodetree conversion. Simplify 64-bit rounding operations to not require double-word arithmetic. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 138 ++++++++++++++++++++------------- 1 file changed, 82 insertions(+), 56 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e59236330a..f4deacd554 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7019,6 +7019,78 @@ static bool do_vec_shift_imm_wide(DisasContext *s, a= rg_qrri_e *a, bool is_u) TRANS(SSHLL_v, do_vec_shift_imm_wide, a, false) TRANS(USHLL_v, do_vec_shift_imm_wide, a, true) =20 +static void gen_sshr_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + assert(shift >=3D 0 && shift <=3D 64); + tcg_gen_sari_i64(dst, src, MIN(shift, 63)); +} + +static void gen_ushr_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + assert(shift >=3D 0 && shift <=3D 64); + if (shift =3D=3D 64) { + tcg_gen_movi_i64(dst, 0); + } else { + tcg_gen_shri_i64(dst, src, shift); + } +} + +static void gen_srshr_bhs(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + assert(shift >=3D 0 && shift <=3D 32); + if (shift) { + TCGv_i64 rnd =3D tcg_constant_i64(1ull << (shift - 1)); + tcg_gen_add_i64(dst, src, rnd); + tcg_gen_sari_i64(dst, dst, shift); + } else { + tcg_gen_mov_i64(dst, src); + } +} + +static void gen_urshr_bhs(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + assert(shift >=3D 0 && shift <=3D 32); + if (shift) { + TCGv_i64 rnd =3D tcg_constant_i64(1ull << (shift - 1)); + tcg_gen_add_i64(dst, src, rnd); + tcg_gen_shri_i64(dst, dst, shift); + } else { + tcg_gen_mov_i64(dst, src); + } +} + +static void gen_srshr_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + assert(shift >=3D 0 && shift <=3D 64); + if (shift =3D=3D 0) { + tcg_gen_mov_i64(dst, src); + } else if (shift =3D=3D 64) { + /* Extension of sign bit (0,-1) plus sign bit (0,1) is zero. */ + tcg_gen_movi_i64(dst, 0); + } else { + TCGv_i64 rnd =3D tcg_temp_new_i64(); + tcg_gen_extract_i64(rnd, src, shift - 1, 1); + tcg_gen_sari_i64(dst, src, shift); + tcg_gen_add_i64(dst, dst, rnd); + } +} + +static void gen_urshr_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + assert(shift >=3D 0 && shift <=3D 64); + if (shift =3D=3D 0) { + tcg_gen_mov_i64(dst, src); + } else if (shift =3D=3D 64) { + /* Rounding will propagate bit 63 into bit 64. */ + tcg_gen_shri_i64(dst, src, 63); + } else { + TCGv_i64 rnd =3D tcg_temp_new_i64(); + tcg_gen_extract_i64(rnd, src, shift - 1, 1); + tcg_gen_shri_i64(dst, src, shift); + tcg_gen_add_i64(dst, dst, rnd); + } +} + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9208,69 +9280,23 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_re= s, TCGv_i64 tcg_src, bool round, bool accumulate, bool is_u, int size, int shift) { - bool extended_result =3D false; - int ext_lshift =3D 0; - TCGv_i64 tcg_src_hi; - - if (round && size =3D=3D 3) { - extended_result =3D true; - ext_lshift =3D 64 - shift; - tcg_src_hi =3D tcg_temp_new_i64(); - } else if (shift =3D=3D 64) { - if (!accumulate && is_u) { - /* result is zero */ - tcg_gen_movi_i64(tcg_res, 0); - return; - } - } - - /* Deal with the rounding step */ - if (round) { - TCGv_i64 tcg_rnd =3D tcg_constant_i64(1ull << (shift - 1)); - if (extended_result) { - TCGv_i64 tcg_zero =3D tcg_constant_i64(0); - if (!is_u) { - /* take care of sign extending tcg_res */ - tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); - tcg_gen_add2_i64(tcg_src, tcg_src_hi, - tcg_src, tcg_src_hi, - tcg_rnd, tcg_zero); - } else { - tcg_gen_add2_i64(tcg_src, tcg_src_hi, - tcg_src, tcg_zero, - tcg_rnd, tcg_zero); - } + if (!round) { + if (is_u) { + gen_ushr_d(tcg_src, tcg_src, shift); } else { - tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); + gen_sshr_d(tcg_src, tcg_src, shift); } - } - - /* Now do the shift right */ - if (round && extended_result) { - /* extended case, >64 bit precision required */ - if (ext_lshift =3D=3D 0) { - /* special case, only high bits matter */ - tcg_gen_mov_i64(tcg_src, tcg_src_hi); + } else if (size =3D=3D MO_64) { + if (is_u) { + gen_urshr_d(tcg_src, tcg_src, shift); } else { - tcg_gen_shri_i64(tcg_src, tcg_src, shift); - tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); - tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); + gen_srshr_d(tcg_src, tcg_src, shift); } } else { if (is_u) { - if (shift =3D=3D 64) { - /* essentially shifting in 64 zeros */ - tcg_gen_movi_i64(tcg_src, 0); - } else { - tcg_gen_shri_i64(tcg_src, tcg_src, shift); - } + gen_urshr_bhs(tcg_src, tcg_src, shift); } else { - if (shift =3D=3D 64) { - /* effectively extending the sign-bit */ - tcg_gen_sari_i64(tcg_src, tcg_src, 63); - } else { - tcg_gen_sari_i64(tcg_src, tcg_src, shift); - } + gen_srshr_bhs(tcg_src, tcg_src, shift); } } =20 --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109061; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109063186116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 95 +++++++++++++++++----------------- target/arm/tcg/a64.decode | 8 +++ 2 files changed, 55 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f4deacd554..8871087af0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7091,6 +7091,51 @@ static void gen_urshr_d(TCGv_i64 dst, TCGv_i64 src, = int64_t shift) } } =20 +static bool do_vec_shift_imm_narrow(DisasContext *s, arg_qrri_e *a, + WideShiftImmFn * const fns[3], MemOp s= ign) +{ + TCGv_i64 tcg_rn, tcg_rd; + int esz =3D a->esz; + int esize; + WideShiftImmFn *fn; + + tcg_debug_assert(esz >=3D MO_8 && esz <=3D MO_32); + + if (!fp_access_check(s)) { + return true; + } + + tcg_rn =3D tcg_temp_new_i64(); + tcg_rd =3D tcg_temp_new_i64(); + tcg_gen_movi_i64(tcg_rd, 0); + + fn =3D fns[esz]; + esize =3D 8 << esz; + for (int i =3D 0, elements =3D 8 >> esz; i < elements; i++) { + read_vec_element(s, tcg_rn, a->rn, i, (esz + 1) | sign); + fn(tcg_rn, tcg_rn, a->imm); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, esize * i, esize); + } + + write_vec_element(s, tcg_rd, a->rd, a->q, MO_64); + clear_vec_high(s, a->q, a->rd); + return true; +} + +static WideShiftImmFn * const shrn_fns[] =3D { + tcg_gen_shri_i64, + tcg_gen_shri_i64, + gen_ushr_d, +}; +TRANS(SHRN_v, do_vec_shift_imm_narrow, a, shrn_fns, 0) + +static WideShiftImmFn * const rshrn_fns[] =3D { + gen_urshr_bhs, + gen_urshr_bhs, + gen_urshr_d, +}; +TRANS(RSHRN_v, do_vec_shift_imm_narrow, a, rshrn_fns, 0) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -10496,52 +10541,6 @@ static void disas_simd_scalar_two_reg_misc(DisasCo= ntext *s, uint32_t insn) } } =20 -/* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ -static void handle_vec_simd_shrn(DisasContext *s, bool is_q, - int immh, int immb, int opcode, int rn, i= nt rd) -{ - int immhb =3D immh << 3 | immb; - int size =3D 32 - clz32(immh) - 1; - int dsize =3D 64; - int esize =3D 8 << size; - int elements =3D dsize/esize; - int shift =3D (2 * esize) - immhb; - bool round =3D extract32(opcode, 0, 1); - TCGv_i64 tcg_rn, tcg_rd, tcg_final; - int i; - - if (extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - tcg_rn =3D tcg_temp_new_i64(); - tcg_rd =3D tcg_temp_new_i64(); - tcg_final =3D tcg_temp_new_i64(); - read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); - - for (i =3D 0; i < elements; i++) { - read_vec_element(s, tcg_rn, rn, i, size+1); - handle_shri_with_rndacc(tcg_rd, tcg_rn, round, - false, true, size+1, shift); - - tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize= ); - } - - if (!is_q) { - write_vec_element(s, tcg_final, rd, 0, MO_64); - } else { - write_vec_element(s, tcg_final, rd, 1, MO_64); - } - - clear_vec_high(s, is_q, rd); -} - - /* AdvSIMD shift by immediate * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 * +---+---+---+-------------+------+------+--------+---+------+------+ @@ -10564,13 +10563,13 @@ static void disas_simd_shift_imm(DisasContext *s,= uint32_t insn) } =20 switch (opcode) { - case 0x10: /* SHRN */ + case 0x10: /* SHRN / SQSHRUN */ case 0x11: /* RSHRN / SQRSHRUN */ if (is_u) { handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, opcode, rn, rd); } else { - handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); + unallocated_encoding(s); } break; case 0x12: /* SQSHRN / UQSHRN */ diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index bf67f8a357..164ed575b9 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1277,3 +1277,11 @@ SSHLL_v 0.00 11110 .... ... 10100 1 ..... ..= ... @q_shli_s USHLL_v 0.10 11110 .... ... 10100 1 ..... ..... @q_shli_b USHLL_v 0.10 11110 .... ... 10100 1 ..... ..... @q_shli_h USHLL_v 0.10 11110 .... ... 10100 1 ..... ..... @q_shli_s + +SHRN_v 0.00 11110 .... ... 10000 1 ..... ..... @q_shri_b +SHRN_v 0.00 11110 .... ... 10000 1 ..... ..... @q_shri_h +SHRN_v 0.00 11110 .... ... 10000 1 ..... ..... @q_shri_s + +RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_b +RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_h +RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_s --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108897; x=1726713697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8xeiwUHFVZW2oDMUKIdwXlsFGkOBW4OXICqeXY8hybQ=; b=W/dFbiPyvXJ65T5Rxv6a5RF5HYhbV+RG+lKuARRqCI4t/tW7HnypJgjbGEIoiDCKtD ahv78mlhSeLrezyodSeKPkybLuZNUGRLRp9yTRw8JbdiI1fvz+9p3G/do4TmScuEUr6W hHbXvG09nxLC78XCjICTEC+Wh13I99uxwtoteIKQnsOUG6oI6cDlXKjhqTH+4btXlV7F zpDtGvIE2vNENtRjgMn6BRrMoGYQPEJkrNvC4doxdLDAxE4BpqKWwFOu/gnjlLZxQbWu gCP7pkmN+NSA7qM0LcP8PAqItYJ3GfCobDrpSb81kXxGrMT9EvassOgfoUlIk/buFeAb G8yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108897; x=1726713697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xeiwUHFVZW2oDMUKIdwXlsFGkOBW4OXICqeXY8hybQ=; b=Gp76/FfYiR1F0e6jj0JpDgzogUMgxD0KJOSCkIErF9fFHO0ydIYpwbyjMxnn0cmwWo Umqp3xX+THWfDScEGfDzVIvWQ4UAF4laXk/O8MEuq4cqYP+F+ShZeY/Cn+UefXiUIDib YfrCp4aIiZbRcGSxRbS1BvOBv3J/yf++oj5mZI7QWArwbTU2tbFIbZ/OtnOrNEFc49AH y0bcvj+nNBXtIuTvSYKs8CB4ruCJxjaP0wHxM3AXG5P7DPK3JQ6cW8Xry5f9PTgSdbHQ Bg2ZGGW21h5P9TxvPJX+hFN1tuSgTO4oAC4mHY6GcHG8sSoBUDCuYuAdLUd8BrN4tm9F x3rg== X-Gm-Message-State: AOJu0Yy5PgVicdfUStXa6ulglV+pjKfSP+Wru+nwu569Lw1oGUerrzXc ow3UtGmzFqvTLTNDKiG74a22asJJC/r8nSoYAxLztxAVYgThF3PQeeEoJ9nciNDu3d+zhOO/Gdt l X-Google-Smtp-Source: AGHT+IGqp8UYi6RgUedxZhHxfJ5FSLns3bWV0aJaQWbJsQXc4f5G9f4tnGmxVRLwwQCyexOg2oxR5Q== X-Received: by 2002:a17:902:db05:b0:206:c12d:abad with SMTP id d9443c01a7336-2076e393e31mr24548035ad.34.1726108897119; Wed, 11 Sep 2024 19:41:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 23/29] target/arm: Convert handle_scalar_simd_shri to decodetree Date: Wed, 11 Sep 2024 19:41:08 -0700 Message-ID: <20240912024114.1097832-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109103413116600 Content-Type: text/plain; charset="utf-8" This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 140 ++++++++++++++++----------------- target/arm/tcg/a64.decode | 16 ++++ 2 files changed, 86 insertions(+), 70 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8871087af0..efd93a7f23 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7035,6 +7035,18 @@ static void gen_ushr_d(TCGv_i64 dst, TCGv_i64 src, i= nt64_t shift) } } =20 +static void gen_ssra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_sshr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + +static void gen_usra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_ushr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + static void gen_srshr_bhs(TCGv_i64 dst, TCGv_i64 src, int64_t shift) { assert(shift >=3D 0 && shift <=3D 32); @@ -7091,6 +7103,27 @@ static void gen_urshr_d(TCGv_i64 dst, TCGv_i64 src, = int64_t shift) } } =20 +static void gen_srsra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_srshr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + +static void gen_ursra_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + gen_urshr_d(src, src, shift); + tcg_gen_add_i64(dst, dst, src); +} + +static void gen_sri_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + /* If shift is 64, dst is unchanged. */ + if (shift !=3D 64) { + tcg_gen_shri_i64(src, src, shift); + tcg_gen_deposit_i64(dst, dst, src, 0, 64 - shift); + } +} + static bool do_vec_shift_imm_narrow(DisasContext *s, arg_qrri_e *a, WideShiftImmFn * const fns[3], MemOp s= ign) { @@ -7136,6 +7169,38 @@ static WideShiftImmFn * const rshrn_fns[] =3D { }; TRANS(RSHRN_v, do_vec_shift_imm_narrow, a, rshrn_fns, 0) =20 +/* + * Advanced SIMD Scalar Shift by Immediate + */ + +static bool do_scalar_shift_imm(DisasContext *s, arg_rri_e *a, + WideShiftImmFn *fn, bool accumulate, + MemOp sign) +{ + if (fp_access_check(s)) { + TCGv_i64 rd =3D tcg_temp_new_i64(); + TCGv_i64 rn =3D tcg_temp_new_i64(); + + read_vec_element(s, rn, a->rn, 0, a->esz | sign); + if (accumulate) { + read_vec_element(s, rd, a->rd, 0, a->esz | sign); + } + fn(rd, rn, a->imm); + write_fp_dreg(s, a->rd, rd); + } + return true; +} + +TRANS(SSHR_s, do_scalar_shift_imm, a, gen_sshr_d, false, 0) +TRANS(USHR_s, do_scalar_shift_imm, a, gen_ushr_d, false, 0) +TRANS(SSRA_s, do_scalar_shift_imm, a, gen_ssra_d, true, 0) +TRANS(USRA_s, do_scalar_shift_imm, a, gen_usra_d, true, 0) +TRANS(SRSHR_s, do_scalar_shift_imm, a, gen_srshr_d, false, 0) +TRANS(URSHR_s, do_scalar_shift_imm, a, gen_urshr_d, false, 0) +TRANS(SRSRA_s, do_scalar_shift_imm, a, gen_srsra_d, true, 0) +TRANS(URSRA_s, do_scalar_shift_imm, a, gen_ursra_d, true, 0) +TRANS(SRI_s, do_scalar_shift_imm, a, gen_sri_d, true, 0) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9352,64 +9417,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res= , TCGv_i64 tcg_src, } } =20 -/* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ -static void handle_scalar_simd_shri(DisasContext *s, - bool is_u, int immh, int immb, - int opcode, int rn, int rd) -{ - const int size =3D 3; - int immhb =3D immh << 3 | immb; - int shift =3D 2 * (8 << size) - immhb; - bool accumulate =3D false; - bool round =3D false; - bool insert =3D false; - TCGv_i64 tcg_rn; - TCGv_i64 tcg_rd; - - if (!extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - switch (opcode) { - case 0x02: /* SSRA / USRA (accumulate) */ - accumulate =3D true; - break; - case 0x04: /* SRSHR / URSHR (rounding) */ - round =3D true; - break; - case 0x06: /* SRSRA / URSRA (accum + rounding) */ - accumulate =3D round =3D true; - break; - case 0x08: /* SRI */ - insert =3D true; - break; - } - - tcg_rn =3D read_fp_dreg(s, rn); - tcg_rd =3D (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new= _i64(); - - if (insert) { - /* shift count same as element size is valid but does nothing; - * special case to avoid potential shift by 64. - */ - int esize =3D 8 << size; - if (shift !=3D esize) { - tcg_gen_shri_i64(tcg_rn, tcg_rn, shift); - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); - } - } else { - handle_shri_with_rndacc(tcg_rd, tcg_rn, round, - accumulate, is_u, size, shift); - } - - write_fp_dreg(s, rd, tcg_rd); -} - /* SHL/SLI - Scalar shift left */ static void handle_scalar_simd_shli(DisasContext *s, bool insert, int immh, int immb, int opcode, @@ -9893,18 +9900,6 @@ static void disas_simd_scalar_shift_imm(DisasContext= *s, uint32_t insn) } =20 switch (opcode) { - case 0x08: /* SRI */ - if (!is_u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x00: /* SSHR / USHR */ - case 0x02: /* SSRA / USRA */ - case 0x04: /* SRSHR / URSHR */ - case 0x06: /* SRSRA / URSRA */ - handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); - break; case 0x0a: /* SHL / SLI */ handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); break; @@ -9940,6 +9935,11 @@ static void disas_simd_scalar_shift_imm(DisasContext= *s, uint32_t insn) handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn,= rd); break; default: + case 0x00: /* SSHR / USHR */ + case 0x02: /* SSRA / USRA */ + case 0x04: /* SRSHR / URSHR */ + case 0x06: /* SRSRA / URSRA */ + case 0x08: /* SRI */ unallocated_encoding(s); break; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 164ed575b9..6c2362b3bb 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -30,6 +30,7 @@ &rri_sf rd rn imm sf &i imm &rr_e rd rn esz +&rri_e rd rn imm esz &rrr_e rd rn rm esz &rrx_e rd rn rm idx esz &rrrr_e rd rn rm ra esz @@ -1285,3 +1286,18 @@ SHRN_v 0.00 11110 .... ... 10000 1 ..... ..= ... @q_shri_s RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_b RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_h RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_s + +# Advanced SIMD scalar shift by immediate + +@shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ + &rri_e esz=3D3 imm=3D%neon_rshift_i6 + +SSHR_s 0101 11110 .... ... 00000 1 ..... ..... @shri_d +USHR_s 0111 11110 .... ... 00000 1 ..... ..... @shri_d +SSRA_s 0101 11110 .... ... 00010 1 ..... ..... @shri_d +USRA_s 0111 11110 .... ... 00010 1 ..... ..... @shri_d +SRSHR_s 0101 11110 .... ... 00100 1 ..... ..... @shri_d +URSHR_s 0111 11110 .... ... 00100 1 ..... ..... @shri_d +SRSRA_s 0101 11110 .... ... 00110 1 ..... ..... @shri_d +URSRA_s 0111 11110 .... ... 00110 1 ..... ..... @shri_d +SRI_s 0111 11110 .... ... 01000 1 ..... ..... @shri_d --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 +++++++--------------------------- target/arm/tcg/a64.decode | 4 ++++ 2 files changed, 13 insertions(+), 35 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index efd93a7f23..934746d2f2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7124,6 +7124,11 @@ static void gen_sri_d(TCGv_i64 dst, TCGv_i64 src, in= t64_t shift) } } =20 +static void gen_sli_d(TCGv_i64 dst, TCGv_i64 src, int64_t shift) +{ + tcg_gen_deposit_i64(dst, dst, src, shift, 64 - shift); +} + static bool do_vec_shift_imm_narrow(DisasContext *s, arg_qrri_e *a, WideShiftImmFn * const fns[3], MemOp s= ign) { @@ -7201,6 +7206,9 @@ TRANS(SRSRA_s, do_scalar_shift_imm, a, gen_srsra_d, t= rue, 0) TRANS(URSRA_s, do_scalar_shift_imm, a, gen_ursra_d, true, 0) TRANS(SRI_s, do_scalar_shift_imm, a, gen_sri_d, true, 0) =20 +TRANS(SHL_s, do_scalar_shift_imm, a, tcg_gen_shli_i64, false, 0) +TRANS(SLI_s, do_scalar_shift_imm, a, gen_sli_d, true, 0) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9417,38 +9425,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res= , TCGv_i64 tcg_src, } } =20 -/* SHL/SLI - Scalar shift left */ -static void handle_scalar_simd_shli(DisasContext *s, bool insert, - int immh, int immb, int opcode, - int rn, int rd) -{ - int size =3D 32 - clz32(immh) - 1; - int immhb =3D immh << 3 | immb; - int shift =3D immhb - (8 << size); - TCGv_i64 tcg_rn; - TCGv_i64 tcg_rd; - - if (!extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - tcg_rn =3D read_fp_dreg(s, rn); - tcg_rd =3D insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); - - if (insert) { - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); - } else { - tcg_gen_shli_i64(tcg_rd, tcg_rn, shift); - } - - write_fp_dreg(s, rd, tcg_rd); -} - /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with * (signed/unsigned) narrowing */ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool i= s_q, @@ -9900,9 +9876,6 @@ static void disas_simd_scalar_shift_imm(DisasContext = *s, uint32_t insn) } =20 switch (opcode) { - case 0x0a: /* SHL / SLI */ - handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); - break; case 0x1c: /* SCVTF, UCVTF */ handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, opcode, rn, rd); @@ -9940,6 +9913,7 @@ static void disas_simd_scalar_shift_imm(DisasContext = *s, uint32_t insn) case 0x04: /* SRSHR / URSHR */ case 0x06: /* SRSRA / URSRA */ case 0x08: /* SRI */ + case 0x0a: /* SHL / SLI */ unallocated_encoding(s); break; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 6c2362b3bb..96803fe6e4 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1291,6 +1291,7 @@ RSHRN_v 0.00 11110 .... ... 10001 1 ..... ...= .. @q_shri_s =20 @shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ &rri_e esz=3D3 imm=3D%neon_rshift_i6 +@shli_d .... ..... 1 imm:6 ..... . rn:5 rd:5 &rri_e esz=3D3=20 =20 SSHR_s 0101 11110 .... ... 00000 1 ..... ..... @shri_d USHR_s 0111 11110 .... ... 00000 1 ..... ..... @shri_d @@ -1301,3 +1302,6 @@ URSHR_s 0111 11110 .... ... 00100 1 ..... ...= .. @shri_d SRSRA_s 0101 11110 .... ... 00110 1 ..... ..... @shri_d URSRA_s 0111 11110 .... ... 00110 1 ..... ..... @shri_d SRI_s 0111 11110 .... ... 01000 1 ..... ..... @shri_d + +SHL_s 0101 11110 .... ... 01010 1 ..... ..... @shli_d +SLI_s 0111 11110 .... ... 01010 1 ..... ..... @shli_d --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1726109070; cv=none; d=zohomail.com; s=zohoarc; b=AJwATZOxEE+d+JXFOTKsspeXab+ocVsV+jNNn+xFnBl6HeqmFGYAk7PKSIxTMEokuWp0yYKnnOvbX7MqHreryfN9rXYK3XV41o3TsiTO1bOqRe4tQq3GolhYvrgSaBvhrqYf3N6UvQXBZrY/YAvTkcgr6tJSWeUi8Lqyd1Q8JsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1726109070; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Qi1Gmkxs9902FcHbK5pM/o/7Unmrs+0ddR9yvY+V3to=; b=WUsHCI13vecyer2c0LohZMrHxr/eEm+1qG7WyHO1f2Yw69BNEVlqzjKHBcju4byqnU/IKlgMHwNCGM2R+A15a9L0i4TRHByqdH4opkrBezhyFDzCHgvRDfDV0LamYG44Tsscuk35KBzTV0UTAcKEfcWNndpHyxTVwwyg+1qRvXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1726109070586825.5132168831283; Wed, 11 Sep 2024 19:44:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1soZms-0007aS-MJ; Wed, 11 Sep 2024 22:42:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1soZmA-0003nm-J8 for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:43 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1soZm8-0004Fu-3p for qemu-devel@nongnu.org; Wed, 11 Sep 2024 22:41:42 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-206bd1c6ccdso5035605ad.3 for ; Wed, 11 Sep 2024 19:41:39 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109071132116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 12 ++++ target/arm/tcg/translate.h | 7 ++ target/arm/tcg/gengvec.c | 36 +++++++++++ target/arm/tcg/neon_helper.c | 33 ++++++++++ target/arm/tcg/translate-neon.c | 110 +------------------------------- target/arm/tcg/neon-dp.decode | 6 +- 6 files changed, 94 insertions(+), 110 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463be38c5..b40589d329 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -324,6 +324,18 @@ DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, voi= d, ptr, ptr, ptr, ptr, i32 DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, pt= r, i32) DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, pt= r, i32) DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, pt= r, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) =20 DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 45990ae292..7721c627e9 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -471,6 +471,13 @@ void gen_neon_sqrshl(unsigned vece, uint32_t rd_ofs, u= int32_t rn_ofs, void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); =20 +void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + int64_t c, uint32_t opr_sz, uint32_t max_sz); +void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + int64_t c, uint32_t opr_sz, uint32_t max_sz); +void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + int64_t c, uint32_t opr_sz, uint32_t max_sz); + void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 3abdc57202..f652520b65 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -1313,6 +1313,42 @@ void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs,= uint32_t rn_ofs, opr_sz, max_sz, 0, fns[vece]); } =20 +void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + int64_t c, uint32_t opr_sz, uint32_t max_sz) +{ + static gen_helper_gvec_2_ptr * const fns[] =3D { + gen_helper_neon_sqshli_b, gen_helper_neon_sqshli_h, + gen_helper_neon_sqshli_s, gen_helper_neon_sqshli_d, + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(c >=3D 0 && c <=3D (8 << vece)); + tcg_gen_gvec_2_ptr(rd_ofs, rn_ofs, tcg_env, opr_sz, max_sz, c, fns[vec= e]); +} + +void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + int64_t c, uint32_t opr_sz, uint32_t max_sz) +{ + static gen_helper_gvec_2_ptr * const fns[] =3D { + gen_helper_neon_uqshli_b, gen_helper_neon_uqshli_h, + gen_helper_neon_uqshli_s, gen_helper_neon_uqshli_d, + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(c >=3D 0 && c <=3D (8 << vece)); + tcg_gen_gvec_2_ptr(rd_ofs, rn_ofs, tcg_env, opr_sz, max_sz, c, fns[vec= e]); +} + +void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + int64_t c, uint32_t opr_sz, uint32_t max_sz) +{ + static gen_helper_gvec_2_ptr * const fns[] =3D { + gen_helper_neon_sqshlui_b, gen_helper_neon_sqshlui_h, + gen_helper_neon_sqshlui_s, gen_helper_neon_sqshlui_d, + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_debug_assert(c >=3D 0 && c <=3D (8 << vece)); + tcg_gen_gvec_2_ptr(rd_ofs, rn_ofs, tcg_env, opr_sz, max_sz, c, fns[vec= e]); +} + void gen_uqadd_bhs(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b, MemO= p esz) { uint64_t max =3D MAKE_64BIT_MASK(0, 8 << esz); diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 082bfd88ad..739e16e441 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -141,6 +141,19 @@ void HELPER(name)(void *vd, void *vn, void *vm, void *= venv, uint32_t desc) \ clear_tail(d, opr_sz, simd_maxsz(desc)); \ } =20 +#define NEON_GVEC_VOP2i_ENV(name, vtype) \ +void HELPER(name)(void *vd, void *vn, void *venv, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + int imm =3D simd_data(desc); \ + vtype *d =3D vd, *n =3D vn; \ + CPUARMState *env =3D venv; \ + for (i =3D 0; i < opr_sz / sizeof(vtype); i++) { \ + NEON_FN(d[i], n[i], imm); \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + /* Pairwise operations. */ /* For 32-bit elements each segment only contains a single element, so the elementwise and pairwise operations are the same. */ @@ -271,22 +284,26 @@ uint64_t HELPER(neon_rshl_u64)(uint64_t val, uint64_t= shift) (dest =3D do_uqrshl_bhs(src1, (int8_t)src2, 8, false, env->vfp.qc)) NEON_VOP_ENV(qshl_u8, neon_u8, 4) NEON_GVEC_VOP2_ENV(neon_uqshl_b, uint8_t) +NEON_GVEC_VOP2i_ENV(neon_uqshli_b, uint8_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_uqrshl_bhs(src1, (int8_t)src2, 16, false, env->vfp.qc)) NEON_VOP_ENV(qshl_u16, neon_u16, 2) NEON_GVEC_VOP2_ENV(neon_uqshl_h, uint16_t) +NEON_GVEC_VOP2i_ENV(neon_uqshli_h, uint16_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_uqrshl_bhs(src1, (int8_t)src2, 32, false, env->vfp.qc)) NEON_GVEC_VOP2_ENV(neon_uqshl_s, uint32_t) +NEON_GVEC_VOP2i_ENV(neon_uqshli_s, uint32_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_uqrshl_d(src1, (int8_t)src2, false, env->vfp.qc)) NEON_GVEC_VOP2_ENV(neon_uqshl_d, uint64_t) +NEON_GVEC_VOP2i_ENV(neon_uqshli_d, uint64_t) #undef NEON_FN =20 uint32_t HELPER(neon_qshl_u32)(CPUARMState *env, uint32_t val, uint32_t sh= ift) @@ -303,22 +320,26 @@ uint64_t HELPER(neon_qshl_u64)(CPUARMState *env, uint= 64_t val, uint64_t shift) (dest =3D do_sqrshl_bhs(src1, (int8_t)src2, 8, false, env->vfp.qc)) NEON_VOP_ENV(qshl_s8, neon_s8, 4) NEON_GVEC_VOP2_ENV(neon_sqshl_b, int8_t) +NEON_GVEC_VOP2i_ENV(neon_sqshli_b, int8_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_sqrshl_bhs(src1, (int8_t)src2, 16, false, env->vfp.qc)) NEON_VOP_ENV(qshl_s16, neon_s16, 2) NEON_GVEC_VOP2_ENV(neon_sqshl_h, int16_t) +NEON_GVEC_VOP2i_ENV(neon_sqshli_h, int16_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_sqrshl_bhs(src1, (int8_t)src2, 32, false, env->vfp.qc)) NEON_GVEC_VOP2_ENV(neon_sqshl_s, int32_t) +NEON_GVEC_VOP2i_ENV(neon_sqshli_s, int32_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_sqrshl_d(src1, (int8_t)src2, false, env->vfp.qc)) NEON_GVEC_VOP2_ENV(neon_sqshl_d, int64_t) +NEON_GVEC_VOP2i_ENV(neon_sqshli_d, int64_t) #undef NEON_FN =20 uint32_t HELPER(neon_qshl_s32)(CPUARMState *env, uint32_t val, uint32_t sh= ift) @@ -334,11 +355,13 @@ uint64_t HELPER(neon_qshl_s64)(CPUARMState *env, uint= 64_t val, uint64_t shift) #define NEON_FN(dest, src1, src2) \ (dest =3D do_suqrshl_bhs(src1, (int8_t)src2, 8, false, env->vfp.qc)) NEON_VOP_ENV(qshlu_s8, neon_s8, 4) +NEON_GVEC_VOP2i_ENV(neon_sqshlui_b, int8_t) #undef NEON_FN =20 #define NEON_FN(dest, src1, src2) \ (dest =3D do_suqrshl_bhs(src1, (int8_t)src2, 16, false, env->vfp.qc)) NEON_VOP_ENV(qshlu_s16, neon_s16, 2) +NEON_GVEC_VOP2i_ENV(neon_sqshlui_h, int16_t) #undef NEON_FN =20 uint32_t HELPER(neon_qshlu_s32)(CPUARMState *env, uint32_t val, uint32_t s= hift) @@ -351,6 +374,16 @@ uint64_t HELPER(neon_qshlu_s64)(CPUARMState *env, uint= 64_t val, uint64_t shift) return do_suqrshl_d(val, (int8_t)shift, false, env->vfp.qc); } =20 +#define NEON_FN(dest, src1, src2) \ + (dest =3D do_suqrshl_bhs(src1, (int8_t)src2, 32, false, env->vfp.qc)) +NEON_GVEC_VOP2i_ENV(neon_sqshlui_s, int32_t) +#undef NEON_FN + +#define NEON_FN(dest, src1, src2) \ + (dest =3D do_suqrshl_d(src1, (int8_t)src2, false, env->vfp.qc)) +NEON_GVEC_VOP2i_ENV(neon_sqshlui_d, int64_t) +#undef NEON_FN + #define NEON_FN(dest, src1, src2) \ (dest =3D do_uqrshl_bhs(src1, (int8_t)src2, 8, true, env->vfp.qc)) NEON_VOP_ENV(qrshl_u8, neon_u8, 4) diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index a31a78c347..6dd70d1c53 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -1101,113 +1101,9 @@ DO_2SH(VRSRA_S, gen_gvec_srsra) DO_2SH(VRSRA_U, gen_gvec_ursra) DO_2SH(VSHR_S, gen_gvec_sshr) DO_2SH(VSHR_U, gen_gvec_ushr) - -static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, - NeonGenTwo64OpEnvFn *fn) -{ - /* - * 2-reg-and-shift operations, size =3D=3D 3 case, where the - * function needs to be passed tcg_env. - */ - TCGv_i64 constimm; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * To avoid excessive duplication of ops we implement shift - * by immediate using the variable shift operations. - */ - constimm =3D tcg_constant_i64(dup_const(a->size, a->shift)); - - for (pass =3D 0; pass < a->q + 1; pass++) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - - read_neon_element64(tmp, a->vm, pass, MO_64); - fn(tmp, tcg_env, tmp, constimm); - write_neon_element64(tmp, a->vd, pass, MO_64); - } - return true; -} - -static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, - NeonGenTwoOpEnvFn *fn) -{ - /* - * 2-reg-and-shift operations, size < 3 case, where the - * helper needs to be passed tcg_env. - */ - TCGv_i32 constimm, tmp; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * To avoid excessive duplication of ops we implement shift - * by immediate using the variable shift operations. - */ - constimm =3D tcg_constant_i32(dup_const(a->size, a->shift)); - tmp =3D tcg_temp_new_i32(); - - for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { - read_neon_element32(tmp, a->vm, pass, MO_32); - fn(tmp, tcg_env, tmp, constimm); - write_neon_element32(tmp, a->vd, pass, MO_32); - } - return true; -} - -#define DO_2SHIFT_ENV(INSN, FUNC) \ - static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ - } \ - static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - static NeonGenTwoOpEnvFn * const fns[] =3D { \ - gen_helper_neon_##FUNC##8, \ - gen_helper_neon_##FUNC##16, \ - gen_helper_neon_##FUNC##32, \ - }; \ - assert(a->size < ARRAY_SIZE(fns)); \ - return do_2shift_env_32(s, a, fns[a->size]); \ - } - -DO_2SHIFT_ENV(VQSHLU, qshlu_s) -DO_2SHIFT_ENV(VQSHL_U, qshl_u) -DO_2SHIFT_ENV(VQSHL_S, qshl_s) +DO_2SH(VQSHLU, gen_neon_sqshlui) +DO_2SH(VQSHL_U, gen_neon_uqshli) +DO_2SH(VQSHL_S, gen_neon_sqshli) =20 static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, NeonGenTwo64OpFn *shiftfn, diff --git a/target/arm/tcg/neon-dp.decode b/target/arm/tcg/neon-dp.decode index 788578c8fa..e883c6ab58 100644 --- a/target/arm/tcg/neon-dp.decode +++ b/target/arm/tcg/neon-dp.decode @@ -291,17 +291,17 @@ VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . = . 1 .... @2reg_shl_s VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b =20 -VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b =20 -VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b =20 -VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2076afe9c61sm5635915ad.231.2024.09.11.19.41.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 19:41:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726108900; x=1726713700; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UfgGIT+vdHS/mRzO6jUdUdMUcxJO8WlE7OmnxSeajyk=; b=gTztqA2jAABfhI9uK3gVrjNGm9sI7WXanJEDqHYI0LEPmrCLVzck0JX3VvMsVUgv45 NYjlHpLwEKjrizkDOD78Tf9sZDA0fFZ+PwDXox/4uew7IrUsM1Fa3uXOtLpi71Ashqs3 H6qmRCenuIFczgTr1PX8CcnGV2aQfaF32rQn8FRIFOyVsu7fzdL8nwi9a3WTraebQ+pu tnMoeCdMtbin+9GTzAlnABgvC8NphOcVA/55bW97adfW6YWuSslln/79ros14d0AWcGM f4EOZ9aPr2p5YztuJ70fZSVbqNzFuhhnkjRUe4vw6jXZg/+ZQT6aZ5ecJx1gB8qfCUrB +IZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726108900; x=1726713700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UfgGIT+vdHS/mRzO6jUdUdMUcxJO8WlE7OmnxSeajyk=; b=E6+EEu199AeOcxDMF8ZuhyerNRFCjmGLS1bJEbmmvBhPvNUHjCBOWVQxXR+tULc+Un G2w5TOVG0037L2Ovn7flnLOq/0uIP1azyvyrj3KfiG3OpfWuSsAvcIEaE8UgFXjbR8No QRZdkQTJXmRp0z/0L63Uv8WrOqthjandhrrZ3EOmrFMUG7lQHePu0VyQvp7Rzr6eTlYX MtFEmRJiwj45bluut1GNlvMaZ1lbm8ulZqXnGcXUrUnaugwSmrNV8U9gHKuz/uyNOqFR IdcKspjwnRXFTi1HPYKJ5vB1G4nln4q+7UdqoutcwtMmCpps7YdO+3tG5ztm3jfYEjFN qDqQ== X-Gm-Message-State: AOJu0YwgBsaLDHXaDHszs15fOz5reE3ljU8eBtAdTT3IoAJj4WSJQeOi lw6OW946OundEk7t145B/+8Gq3PoQfZeammp6P+HWcaRBtldXzFqYBCT7gCAeaDqvEKgfuSPXaB U X-Google-Smtp-Source: AGHT+IHmDlgWTHDgkYQV+aX61ORPFZOPOit3FdgXu9G9kG+QFUOgAZiuwNh9ty9+deUbdmOWZaCD/g== X-Received: by 2002:a17:902:cf42:b0:202:3711:6fe9 with SMTP id d9443c01a7336-2076e4485fbmr17334895ad.51.1726108899471; Wed, 11 Sep 2024 19:41:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 26/29] target/arm: Widen NeonGenNarrowEnvFn return to 64 bits Date: Wed, 11 Sep 2024 19:41:11 -0700 Message-ID: <20240912024114.1097832-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240912024114.1097832-1-richard.henderson@linaro.org> References: <20240912024114.1097832-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109197651116600 Content-Type: text/plain; charset="utf-8" While these functions really do return a 32-bit value, widening the return type means that we need do less marshalling between TCG types. Remove NeonGenNarrowEnvFn typedef; add NeonGenOne64OpEnvFn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 22 ++++++------ target/arm/tcg/translate.h | 2 +- target/arm/tcg/neon_helper.c | 43 ++++++++++++++--------- target/arm/tcg/translate-a64.c | 60 ++++++++++++++++++--------------- target/arm/tcg/translate-neon.c | 44 ++++++++++++------------ 5 files changed, 93 insertions(+), 78 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b40589d329..58919b670e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -375,17 +375,17 @@ DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) =20 -DEF_HELPER_1(neon_narrow_u8, i32, i64) -DEF_HELPER_1(neon_narrow_u16, i32, i64) -DEF_HELPER_2(neon_unarrow_sat8, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64) -DEF_HELPER_2(neon_unarrow_sat16, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64) -DEF_HELPER_2(neon_unarrow_sat32, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64) +DEF_HELPER_1(neon_narrow_u8, i64, i64) +DEF_HELPER_1(neon_narrow_u16, i64, i64) +DEF_HELPER_2(neon_unarrow_sat8, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u8, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s8, i64, env, i64) +DEF_HELPER_2(neon_unarrow_sat16, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u16, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s16, i64, env, i64) +DEF_HELPER_2(neon_unarrow_sat32, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u32, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s32, i64, env, i64) DEF_HELPER_1(neon_narrow_high_u8, i32, i64) DEF_HELPER_1(neon_narrow_high_u16, i32, i64) DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 7721c627e9..5a2e10d64d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -605,13 +605,13 @@ typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, = TCGv_i32, typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); -typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); +typedef void NeonGenOne64OpEnvFn(TCGv_i64, TCGv_env, TCGv_i64); typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 739e16e441..93b2076c64 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -598,13 +598,15 @@ NEON_VOP_ENV(qrdmulh_s32, neon_s32, 1) #undef NEON_FN #undef NEON_QDMULH32 =20 -uint32_t HELPER(neon_narrow_u8)(uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_u8)(uint64_t x) { return (x & 0xffu) | ((x >> 8) & 0xff00u) | ((x >> 16) & 0xff0000u) | ((x >> 24) & 0xff000000u); } =20 -uint32_t HELPER(neon_narrow_u16)(uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_u16)(uint64_t x) { return (x & 0xffffu) | ((x >> 16) & 0xffff0000u); } @@ -635,7 +637,8 @@ uint32_t HELPER(neon_narrow_round_high_u16)(uint64_t x) return ((x >> 16) & 0xffff) | ((x >> 32) & 0xffff0000); } =20 -uint32_t HELPER(neon_unarrow_sat8)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_unarrow_sat8)(CPUARMState *env, uint64_t x) { uint16_t s; uint8_t d; @@ -662,7 +665,8 @@ uint32_t HELPER(neon_unarrow_sat8)(CPUARMState *env, ui= nt64_t x) return res; } =20 -uint32_t HELPER(neon_narrow_sat_u8)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_sat_u8)(CPUARMState *env, uint64_t x) { uint16_t s; uint8_t d; @@ -685,7 +689,8 @@ uint32_t HELPER(neon_narrow_sat_u8)(CPUARMState *env, u= int64_t x) return res; } =20 -uint32_t HELPER(neon_narrow_sat_s8)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_sat_s8)(CPUARMState *env, uint64_t x) { int16_t s; uint8_t d; @@ -708,7 +713,8 @@ uint32_t HELPER(neon_narrow_sat_s8)(CPUARMState *env, u= int64_t x) return res; } =20 -uint32_t HELPER(neon_unarrow_sat16)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_unarrow_sat16)(CPUARMState *env, uint64_t x) { uint32_t high; uint32_t low; @@ -728,10 +734,11 @@ uint32_t HELPER(neon_unarrow_sat16)(CPUARMState *env,= uint64_t x) high =3D 0xffff; SET_QC(); } - return low | (high << 16); + return deposit32(low, 16, 16, high); } =20 -uint32_t HELPER(neon_narrow_sat_u16)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_sat_u16)(CPUARMState *env, uint64_t x) { uint32_t high; uint32_t low; @@ -745,10 +752,11 @@ uint32_t HELPER(neon_narrow_sat_u16)(CPUARMState *env= , uint64_t x) high =3D 0xffff; SET_QC(); } - return low | (high << 16); + return deposit32(low, 16, 16, high); } =20 -uint32_t HELPER(neon_narrow_sat_s16)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_sat_s16)(CPUARMState *env, uint64_t x) { int32_t low; int32_t high; @@ -762,10 +770,11 @@ uint32_t HELPER(neon_narrow_sat_s16)(CPUARMState *env= , uint64_t x) high =3D (high >> 31) ^ 0x7fff; SET_QC(); } - return (uint16_t)low | (high << 16); + return deposit32(low, 16, 16, high); } =20 -uint32_t HELPER(neon_unarrow_sat32)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_unarrow_sat32)(CPUARMState *env, uint64_t x) { if (x & 0x8000000000000000ull) { SET_QC(); @@ -778,7 +787,8 @@ uint32_t HELPER(neon_unarrow_sat32)(CPUARMState *env, u= int64_t x) return x; } =20 -uint32_t HELPER(neon_narrow_sat_u32)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_sat_u32)(CPUARMState *env, uint64_t x) { if (x > 0xffffffffu) { SET_QC(); @@ -787,13 +797,14 @@ uint32_t HELPER(neon_narrow_sat_u32)(CPUARMState *env= , uint64_t x) return x; } =20 -uint32_t HELPER(neon_narrow_sat_s32)(CPUARMState *env, uint64_t x) +/* Only the low 32-bits of output are significant. */ +uint64_t HELPER(neon_narrow_sat_s32)(CPUARMState *env, uint64_t x) { if ((int64_t)x !=3D (int32_t)x) { SET_QC(); - return ((int64_t)x >> 63) ^ 0x7fffffff; + return (uint32_t)((int64_t)x >> 63) ^ 0x7fffffff; } - return x; + return (uint32_t)x; } =20 uint64_t HELPER(neon_widen_u8)(uint32_t x) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 934746d2f2..7918720d9b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -9439,11 +9439,9 @@ static void handle_vec_simd_sqshrn(DisasContext *s, = bool is_scalar, bool is_q, int elements =3D is_scalar ? 1 : (64 / esize); bool round =3D extract32(opcode, 0, 1); MemOp ldop =3D (size + 1) | (is_u_shift ? 0 : MO_SIGN); - TCGv_i64 tcg_rn, tcg_rd; - TCGv_i32 tcg_rd_narrowed; - TCGv_i64 tcg_final; + TCGv_i64 tcg_rn, tcg_rd, tcg_final; =20 - static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] =3D { + static NeonGenOne64OpEnvFn * const signed_narrow_fns[4][2] =3D { { gen_helper_neon_narrow_sat_s8, gen_helper_neon_unarrow_sat8 }, { gen_helper_neon_narrow_sat_s16, @@ -9452,13 +9450,13 @@ static void handle_vec_simd_sqshrn(DisasContext *s,= bool is_scalar, bool is_q, gen_helper_neon_unarrow_sat32 }, { NULL, NULL }, }; - static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] =3D { + static NeonGenOne64OpEnvFn * const unsigned_narrow_fns[4] =3D { gen_helper_neon_narrow_sat_u8, gen_helper_neon_narrow_sat_u16, gen_helper_neon_narrow_sat_u32, NULL }; - NeonGenNarrowEnvFn *narrowfn; + NeonGenOne64OpEnvFn *narrowfn; =20 int i; =20 @@ -9481,15 +9479,13 @@ static void handle_vec_simd_sqshrn(DisasContext *s,= bool is_scalar, bool is_q, =20 tcg_rn =3D tcg_temp_new_i64(); tcg_rd =3D tcg_temp_new_i64(); - tcg_rd_narrowed =3D tcg_temp_new_i32(); tcg_final =3D tcg_temp_new_i64(); =20 for (i =3D 0; i < elements; i++) { read_vec_element(s, tcg_rn, rn, i, ldop); handle_shri_with_rndacc(tcg_rd, tcg_rn, round, false, is_u_shift, size+1, shift); - narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd); - tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); + narrowfn(tcg_rd, tcg_env, tcg_rd); if (i =3D=3D 0) { tcg_gen_extract_i64(tcg_final, tcg_rd, 0, esize); } else { @@ -10228,35 +10224,35 @@ static void handle_2misc_narrow(DisasContext *s, = bool scalar, * in the source becomes a size element in the destination). */ int pass; - TCGv_i32 tcg_res[2]; + TCGv_i64 tcg_res[2]; int destelt =3D is_q ? 2 : 0; int passes =3D scalar ? 1 : 2; =20 if (scalar) { - tcg_res[1] =3D tcg_constant_i32(0); + tcg_res[1] =3D tcg_constant_i64(0); } =20 for (pass =3D 0; pass < passes; pass++) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); - NeonGenNarrowFn *genfn =3D NULL; - NeonGenNarrowEnvFn *genenvfn =3D NULL; + NeonGenOne64OpFn *genfn =3D NULL; + NeonGenOne64OpEnvFn *genenvfn =3D NULL; =20 if (scalar) { read_vec_element(s, tcg_op, rn, pass, size + 1); } else { read_vec_element(s, tcg_op, rn, pass, MO_64); } - tcg_res[pass] =3D tcg_temp_new_i32(); + tcg_res[pass] =3D tcg_temp_new_i64(); =20 switch (opcode) { case 0x12: /* XTN, SQXTUN */ { - static NeonGenNarrowFn * const xtnfns[3] =3D { + static NeonGenOne64OpFn * const xtnfns[3] =3D { gen_helper_neon_narrow_u8, gen_helper_neon_narrow_u16, - tcg_gen_extrl_i64_i32, + tcg_gen_ext32u_i64, }; - static NeonGenNarrowEnvFn * const sqxtunfns[3] =3D { + static NeonGenOne64OpEnvFn * const sqxtunfns[3] =3D { gen_helper_neon_unarrow_sat8, gen_helper_neon_unarrow_sat16, gen_helper_neon_unarrow_sat32, @@ -10270,7 +10266,7 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, } case 0x14: /* SQXTN, UQXTN */ { - static NeonGenNarrowEnvFn * const fns[3][2] =3D { + static NeonGenOne64OpEnvFn * const fns[3][2] =3D { { gen_helper_neon_narrow_sat_s8, gen_helper_neon_narrow_sat_u8 }, { gen_helper_neon_narrow_sat_s16, @@ -10284,7 +10280,9 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, case 0x16: /* FCVTN, FCVTN2 */ /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ if (size =3D=3D 2) { - gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, tcg_env); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + gen_helper_vfp_fcvtsd(tmp, tcg_op, tcg_env); + tcg_gen_extu_i32_i64(tcg_res[pass], tmp); } else { TCGv_i32 tcg_lo =3D tcg_temp_new_i32(); TCGv_i32 tcg_hi =3D tcg_temp_new_i32(); @@ -10294,21 +10292,29 @@ static void handle_2misc_narrow(DisasContext *s, = bool scalar, tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op); gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); - tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); + tcg_gen_deposit_i32(tcg_lo, tcg_lo, tcg_hi, 16, 16); + tcg_gen_extu_i32_i64(tcg_res[pass], tcg_lo); } break; case 0x36: /* BFCVTN, BFCVTN2 */ { TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); - gen_helper_bfcvt_pair(tcg_res[pass], tcg_op, fpst); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + gen_helper_bfcvt_pair(tmp, tcg_op, fpst); + tcg_gen_extu_i32_i64(tcg_res[pass], tmp); } break; case 0x56: /* FCVTXN, FCVTXN2 */ - /* 64 bit to 32 bit float conversion - * with von Neumann rounding (round to odd) - */ - assert(size =3D=3D 2); - gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, tcg_env); + { + /* + * 64 bit to 32 bit float conversion + * with von Neumann rounding (round to odd) + */ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + assert(size =3D=3D 2); + gen_helper_fcvtx_f64_to_f32(tmp, tcg_op, tcg_env); + tcg_gen_extu_i32_i64(tcg_res[pass], tmp); + } break; default: g_assert_not_reached(); @@ -10322,7 +10328,7 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, } =20 for (pass =3D 0; pass < 2; pass++) { - write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); + write_vec_element(s, tcg_res[pass], rd, destelt + pass, MO_32); } clear_vec_high(s, is_q, rd); } diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 6dd70d1c53..9c8829ad7d 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -1107,11 +1107,10 @@ DO_2SH(VQSHL_S, gen_neon_sqshli) =20 static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, NeonGenTwo64OpFn *shiftfn, - NeonGenNarrowEnvFn *narrowfn) + NeonGenOne64OpEnvFn *narrowfn) { /* 2-reg-and-shift narrowing-shift operations, size =3D=3D 3 case */ - TCGv_i64 constimm, rm1, rm2; - TCGv_i32 rd; + TCGv_i64 constimm, rm1, rm2, rd; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -1138,7 +1137,7 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_= 2reg_shift *a, constimm =3D tcg_constant_i64(-a->shift); rm1 =3D tcg_temp_new_i64(); rm2 =3D tcg_temp_new_i64(); - rd =3D tcg_temp_new_i32(); + rd =3D tcg_temp_new_i64(); =20 /* Load both inputs first to avoid potential overwrite if rm =3D=3D rd= */ read_neon_element64(rm1, a->vm, 0, MO_64); @@ -1146,18 +1145,18 @@ static bool do_2shift_narrow_64(DisasContext *s, ar= g_2reg_shift *a, =20 shiftfn(rm1, rm1, constimm); narrowfn(rd, tcg_env, rm1); - write_neon_element32(rd, a->vd, 0, MO_32); + write_neon_element64(rd, a->vd, 0, MO_32); =20 shiftfn(rm2, rm2, constimm); narrowfn(rd, tcg_env, rm2); - write_neon_element32(rd, a->vd, 1, MO_32); + write_neon_element64(rd, a->vd, 1, MO_32); =20 return true; } =20 static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, NeonGenTwoOpFn *shiftfn, - NeonGenNarrowEnvFn *narrowfn) + NeonGenOne64OpEnvFn *narrowfn) { /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ TCGv_i32 constimm, rm1, rm2, rm3, rm4; @@ -1212,16 +1211,16 @@ static bool do_2shift_narrow_32(DisasContext *s, ar= g_2reg_shift *a, =20 tcg_gen_concat_i32_i64(rtmp, rm1, rm2); =20 - narrowfn(rm1, tcg_env, rtmp); - write_neon_element32(rm1, a->vd, 0, MO_32); + narrowfn(rtmp, tcg_env, rtmp); + write_neon_element64(rtmp, a->vd, 0, MO_32); =20 shiftfn(rm3, rm3, constimm); shiftfn(rm4, rm4, constimm); =20 tcg_gen_concat_i32_i64(rtmp, rm3, rm4); =20 - narrowfn(rm3, tcg_env, rtmp); - write_neon_element32(rm3, a->vd, 1, MO_32); + narrowfn(rtmp, tcg_env, rtmp); + write_neon_element64(rtmp, a->vd, 1, MO_32); return true; } =20 @@ -1236,17 +1235,17 @@ static bool do_2shift_narrow_32(DisasContext *s, ar= g_2reg_shift *a, return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ } =20 -static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +static void gen_neon_narrow_u32(TCGv_i64 dest, TCGv_ptr env, TCGv_i64 src) { - tcg_gen_extrl_i64_i32(dest, src); + tcg_gen_ext32u_i64(dest, src); } =20 -static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +static void gen_neon_narrow_u16(TCGv_i64 dest, TCGv_ptr env, TCGv_i64 src) { gen_helper_neon_narrow_u16(dest, src); } =20 -static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +static void gen_neon_narrow_u8(TCGv_i64 dest, TCGv_ptr env, TCGv_i64 src) { gen_helper_neon_narrow_u8(dest, src); } @@ -2837,10 +2836,9 @@ static bool trans_VZIP(DisasContext *s, arg_2misc *a) } =20 static bool do_vmovn(DisasContext *s, arg_2misc *a, - NeonGenNarrowEnvFn *narrowfn) + NeonGenOne64OpEnvFn *narrowfn) { - TCGv_i64 rm; - TCGv_i32 rd0, rd1; + TCGv_i64 rm, rd0, rd1; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -2865,22 +2863,22 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, } =20 rm =3D tcg_temp_new_i64(); - rd0 =3D tcg_temp_new_i32(); - rd1 =3D tcg_temp_new_i32(); + rd0 =3D tcg_temp_new_i64(); + rd1 =3D tcg_temp_new_i64(); =20 read_neon_element64(rm, a->vm, 0, MO_64); narrowfn(rd0, tcg_env, rm); read_neon_element64(rm, a->vm, 1, MO_64); narrowfn(rd1, tcg_env, rm); - write_neon_element32(rd0, a->vd, 0, MO_32); - write_neon_element32(rd1, a->vd, 1, MO_32); + write_neon_element64(rd0, a->vd, 0, MO_32); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109149583116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 223 ++++++++++++++------------------- target/arm/tcg/a64.decode | 36 +++++- 2 files changed, 128 insertions(+), 131 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7918720d9b..77324e0145 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6982,6 +6982,9 @@ TRANS(URSRA_v, do_vec_shift_imm, a, gen_gvec_ursra) TRANS(SRI_v, do_vec_shift_imm, a, gen_gvec_sri) TRANS(SHL_v, do_vec_shift_imm, a, tcg_gen_gvec_shli) TRANS(SLI_v, do_vec_shift_imm, a, gen_gvec_sli); +TRANS(SQSHL_vi, do_vec_shift_imm, a, gen_neon_sqshli) +TRANS(UQSHL_vi, do_vec_shift_imm, a, gen_neon_uqshli) +TRANS(SQSHLU_vi, do_vec_shift_imm, a, gen_neon_sqshlui) =20 static bool do_vec_shift_imm_wide(DisasContext *s, arg_qrri_e *a, bool is_= u) { @@ -7209,6 +7212,92 @@ TRANS(SRI_s, do_scalar_shift_imm, a, gen_sri_d, true= , 0) TRANS(SHL_s, do_scalar_shift_imm, a, tcg_gen_shli_i64, false, 0) TRANS(SLI_s, do_scalar_shift_imm, a, gen_sli_d, true, 0) =20 +static void trunc_i64_env_imm(TCGv_i64 d, TCGv_i64 s, int64_t i, + NeonGenTwoOpEnvFn *fn) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t, s); + fn(t, tcg_env, t, tcg_constant_i32(i)); + tcg_gen_extu_i32_i64(d, t); +} + +static void gen_sqshli_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshl_s8); +} + +static void gen_sqshli_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshl_s16); +} + +static void gen_sqshli_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshl_s32); +} + +static void gen_sqshli_d(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_helper_neon_qshl_s64(d, tcg_env, s, tcg_constant_i64(i)); +} + +static void gen_uqshli_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshl_u8); +} + +static void gen_uqshli_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshl_u16); +} + +static void gen_uqshli_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshl_u32); +} + +static void gen_uqshli_d(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_helper_neon_qshl_u64(d, tcg_env, s, tcg_constant_i64(i)); +} + +static void gen_sqshlui_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshlu_s8); +} + +static void gen_sqshlui_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshlu_s16); +} + +static void gen_sqshlui_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + trunc_i64_env_imm(d, s, i, gen_helper_neon_qshlu_s32); +} + +static void gen_sqshlui_d(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_helper_neon_qshlu_s64(d, tcg_env, s, tcg_constant_i64(i)); +} + +static WideShiftImmFn * const f_scalar_sqshli[] =3D { + gen_sqshli_b, gen_sqshli_h, gen_sqshli_s, gen_sqshli_d +}; + +static WideShiftImmFn * const f_scalar_uqshli[] =3D { + gen_uqshli_b, gen_uqshli_h, gen_uqshli_s, gen_uqshli_d +}; + +static WideShiftImmFn * const f_scalar_sqshlui[] =3D { + gen_sqshlui_b, gen_sqshlui_h, gen_sqshlui_s, gen_sqshlui_d +}; + +/* Note that the helpers sign-extend their inputs, so don't do it here. */ +TRANS(SQSHL_si, do_scalar_shift_imm, a, f_scalar_sqshli[a->esz], false, 0) +TRANS(UQSHL_si, do_scalar_shift_imm, a, f_scalar_uqshli[a->esz], false, 0) +TRANS(SQSHLU_si, do_scalar_shift_imm, a, f_scalar_sqshlui[a->esz], false, = 0) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9501,116 +9590,6 @@ static void handle_vec_simd_sqshrn(DisasContext *s,= bool is_scalar, bool is_q, clear_vec_high(s, is_q, rd); } =20 -/* SQSHLU, UQSHL, SQSHL: saturating left shifts */ -static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, - bool src_unsigned, bool dst_unsigned, - int immh, int immb, int rn, int rd) -{ - int immhb =3D immh << 3 | immb; - int size =3D 32 - clz32(immh) - 1; - int shift =3D immhb - (8 << size); - int pass; - - assert(immh !=3D 0); - assert(!(scalar && is_q)); - - if (!scalar) { - if (!is_q && extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - /* Since we use the variable-shift helpers we must - * replicate the shift count into each element of - * the tcg_shift value. - */ - switch (size) { - case 0: - shift |=3D shift << 8; - /* fall through */ - case 1: - shift |=3D shift << 16; - break; - case 2: - case 3: - break; - default: - g_assert_not_reached(); - } - } - - if (!fp_access_check(s)) { - return; - } - - if (size =3D=3D 3) { - TCGv_i64 tcg_shift =3D tcg_constant_i64(shift); - static NeonGenTwo64OpEnvFn * const fns[2][2] =3D { - { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, - { NULL, gen_helper_neon_qshl_u64 }, - }; - NeonGenTwo64OpEnvFn *genfn =3D fns[src_unsigned][dst_unsigned]; - int maxpass =3D is_q ? 2 : 1; - - for (pass =3D 0; pass < maxpass; pass++) { - TCGv_i64 tcg_op =3D tcg_temp_new_i64(); - - read_vec_element(s, tcg_op, rn, pass, MO_64); - genfn(tcg_op, tcg_env, tcg_op, tcg_shift); - write_vec_element(s, tcg_op, rd, pass, MO_64); - } - clear_vec_high(s, is_q, rd); - } else { - TCGv_i32 tcg_shift =3D tcg_constant_i32(shift); - static NeonGenTwoOpEnvFn * const fns[2][2][3] =3D { - { - { gen_helper_neon_qshl_s8, - gen_helper_neon_qshl_s16, - gen_helper_neon_qshl_s32 }, - { gen_helper_neon_qshlu_s8, - gen_helper_neon_qshlu_s16, - gen_helper_neon_qshlu_s32 } - }, { - { NULL, NULL, NULL }, - { gen_helper_neon_qshl_u8, - gen_helper_neon_qshl_u16, - gen_helper_neon_qshl_u32 } - } - }; - NeonGenTwoOpEnvFn *genfn =3D fns[src_unsigned][dst_unsigned][size]; - MemOp memop =3D scalar ? size : MO_32; - int maxpass =3D scalar ? 1 : is_q ? 4 : 2; - - for (pass =3D 0; pass < maxpass; pass++) { - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); - - read_vec_element_i32(s, tcg_op, rn, pass, memop); - genfn(tcg_op, tcg_env, tcg_op, tcg_shift); - if (scalar) { - switch (size) { - case 0: - tcg_gen_ext8u_i32(tcg_op, tcg_op); - break; - case 1: - tcg_gen_ext16u_i32(tcg_op, tcg_op); - break; - case 2: - break; - default: - g_assert_not_reached(); - } - write_fp_sreg(s, rd, tcg_op); - } else { - write_vec_element_i32(s, tcg_op, rd, pass, MO_32); - } - } - - if (!scalar) { - clear_vec_high(s, is_q, rd); - } - } -} - /* Common vector code for handling integer to FP conversion */ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, int elements, int is_signed, @@ -9890,16 +9869,6 @@ static void disas_simd_scalar_shift_imm(DisasContext= *s, uint32_t insn) handle_vec_simd_sqshrn(s, true, false, is_u, is_u, immh, immb, opcode, rn, rd); break; - case 0xc: /* SQSHLU */ - if (!is_u) { - unallocated_encoding(s); - return; - } - handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); - break; - case 0xe: /* SQSHL, UQSHL */ - handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); - break; case 0x1f: /* FCVTZS, FCVTZU */ handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn,= rd); break; @@ -9910,6 +9879,8 @@ static void disas_simd_scalar_shift_imm(DisasContext = *s, uint32_t insn) case 0x06: /* SRSRA / URSRA */ case 0x08: /* SRI */ case 0x0a: /* SHL / SLI */ + case 0x0c: /* SQSHLU */ + case 0x0e: /* SQSHL, UQSHL */ unallocated_encoding(s); break; } @@ -10561,16 +10532,6 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, opcode, rn, rd); break; - case 0xc: /* SQSHLU */ - if (!is_u) { - unallocated_encoding(s); - return; - } - handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); - break; - case 0xe: /* SQSHL, UQSHL */ - handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); - break; case 0x1f: /* FCVTZS/ FCVTZU */ handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn,= rd); return; @@ -10581,6 +10542,8 @@ static void disas_simd_shift_imm(DisasContext *s, u= int32_t insn) case 0x06: /* SRSRA / URSRA (accum + rounding) */ case 0x08: /* SRI */ case 0x0a: /* SHL / SLI */ + case 0x0c: /* SQSHLU */ + case 0x0e: /* SQSHL, UQSHL */ case 0x14: /* SSHLL / USHLL */ unallocated_encoding(s); return; diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 96803fe6e4..63e04ddfcd 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1287,11 +1287,30 @@ RSHRN_v 0.00 11110 .... ... 10001 1 ..... .= .... @q_shri_b RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_h RSHRN_v 0.00 11110 .... ... 10001 1 ..... ..... @q_shri_s =20 +SQSHL_vi 0.00 11110 .... ... 01110 1 ..... ..... @q_shli_b +SQSHL_vi 0.00 11110 .... ... 01110 1 ..... ..... @q_shli_h +SQSHL_vi 0.00 11110 .... ... 01110 1 ..... ..... @q_shli_s +SQSHL_vi 0.00 11110 .... ... 01110 1 ..... ..... @q_shli_d + +UQSHL_vi 0.10 11110 .... ... 01110 1 ..... ..... @q_shli_b +UQSHL_vi 0.10 11110 .... ... 01110 1 ..... ..... @q_shli_h +UQSHL_vi 0.10 11110 .... ... 01110 1 ..... ..... @q_shli_s +UQSHL_vi 0.10 11110 .... ... 01110 1 ..... ..... @q_shli_d + +SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..... @q_shli_b +SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..... @q_shli_h +SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..... @q_shli_s +SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..... @q_shli_d + # Advanced SIMD scalar shift by immediate =20 @shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ &rri_e esz=3D3 imm=3D%neon_rshift_i6 -@shli_d .... ..... 1 imm:6 ..... . rn:5 rd:5 &rri_e esz=3D3=20 + +@shli_b .... ..... 0001 imm:3 ..... . rn:5 rd:5 &rri_e esz=3D0 +@shli_h .... ..... 001 imm:4 ..... . rn:5 rd:5 &rri_e esz=3D1 +@shli_s .... ..... 01 imm:5 ..... . rn:5 rd:5 &rri_e esz=3D2 +@shli_d .... ..... 1 imm:6 ..... . rn:5 rd:5 &rri_e esz=3D3 =20 SSHR_s 0101 11110 .... ... 00000 1 ..... ..... @shri_d USHR_s 0111 11110 .... ... 00000 1 ..... ..... @shri_d @@ -1305,3 +1324,18 @@ SRI_s 0111 11110 .... ... 01000 1 ..... ..= ... @shri_d =20 SHL_s 0101 11110 .... ... 01010 1 ..... ..... @shli_d SLI_s 0111 11110 .... ... 01010 1 ..... ..... @shli_d + +SQSHL_si 0101 11110 .... ... 01110 1 ..... ..... @shli_b +SQSHL_si 0101 11110 .... ... 01110 1 ..... ..... @shli_h +SQSHL_si 0101 11110 .... ... 01110 1 ..... ..... @shli_s +SQSHL_si 0101 11110 .... ... 01110 1 ..... ..... @shli_d + +UQSHL_si 0111 11110 .... ... 01110 1 ..... ..... @shli_b +UQSHL_si 0111 11110 .... ... 01110 1 ..... ..... @shli_h +UQSHL_si 0111 11110 .... ... 01110 1 ..... ..... @shli_s +UQSHL_si 0111 11110 .... ... 01110 1 ..... ..... @shli_d + +SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_b +SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_h +SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_s +SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_d --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109045042116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 176 ++++++++++++++++++++++++++++++--- target/arm/tcg/a64.decode | 24 +++++ 2 files changed, 186 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 77324e0145..e6290e1145 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7163,6 +7163,122 @@ static bool do_vec_shift_imm_narrow(DisasContext *s= , arg_qrri_e *a, return true; } =20 +static void gen_sqshrn_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + tcg_gen_sari_i64(d, s, i); + tcg_gen_ext16u_i64(d, d); + gen_helper_neon_narrow_sat_s8(d, tcg_env, d); +} + +static void gen_sqshrn_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + tcg_gen_sari_i64(d, s, i); + tcg_gen_ext32u_i64(d, d); + gen_helper_neon_narrow_sat_s16(d, tcg_env, d); +} + +static void gen_sqshrn_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_sshr_d(d, s, i); + gen_helper_neon_narrow_sat_s32(d, tcg_env, d); +} + +static void gen_uqshrn_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + tcg_gen_shri_i64(d, s, i); + gen_helper_neon_narrow_sat_u8(d, tcg_env, d); +} + +static void gen_uqshrn_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + tcg_gen_shri_i64(d, s, i); + gen_helper_neon_narrow_sat_u16(d, tcg_env, d); +} + +static void gen_uqshrn_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_ushr_d(d, s, i); + gen_helper_neon_narrow_sat_u32(d, tcg_env, d); +} + +static void gen_sqshrun_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + tcg_gen_sari_i64(d, s, i); + tcg_gen_ext16u_i64(d, d); + gen_helper_neon_unarrow_sat8(d, tcg_env, d); +} + +static void gen_sqshrun_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + tcg_gen_sari_i64(d, s, i); + tcg_gen_ext32u_i64(d, d); + gen_helper_neon_unarrow_sat16(d, tcg_env, d); +} + +static void gen_sqshrun_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_sshr_d(d, s, i); + gen_helper_neon_unarrow_sat32(d, tcg_env, d); +} + +static void gen_sqrshrn_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_srshr_bhs(d, s, i); + tcg_gen_ext16u_i64(d, d); + gen_helper_neon_narrow_sat_s8(d, tcg_env, d); +} + +static void gen_sqrshrn_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_srshr_bhs(d, s, i); + tcg_gen_ext32u_i64(d, d); + gen_helper_neon_narrow_sat_s16(d, tcg_env, d); +} + +static void gen_sqrshrn_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_srshr_d(d, s, i); + gen_helper_neon_narrow_sat_s32(d, tcg_env, d); +} + +static void gen_uqrshrn_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_urshr_bhs(d, s, i); + gen_helper_neon_narrow_sat_u8(d, tcg_env, d); +} + +static void gen_uqrshrn_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_urshr_bhs(d, s, i); + gen_helper_neon_narrow_sat_u16(d, tcg_env, d); +} + +static void gen_uqrshrn_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_urshr_d(d, s, i); + gen_helper_neon_narrow_sat_u32(d, tcg_env, d); +} + +static void gen_sqrshrun_b(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_srshr_bhs(d, s, i); + tcg_gen_ext16u_i64(d, d); + gen_helper_neon_unarrow_sat8(d, tcg_env, d); +} + +static void gen_sqrshrun_h(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_srshr_bhs(d, s, i); + tcg_gen_ext32u_i64(d, d); + gen_helper_neon_unarrow_sat16(d, tcg_env, d); +} + +static void gen_sqrshrun_s(TCGv_i64 d, TCGv_i64 s, int64_t i) +{ + gen_srshr_d(d, s, i); + gen_helper_neon_unarrow_sat32(d, tcg_env, d); +} + static WideShiftImmFn * const shrn_fns[] =3D { tcg_gen_shri_i64, tcg_gen_shri_i64, @@ -7177,6 +7293,48 @@ static WideShiftImmFn * const rshrn_fns[] =3D { }; TRANS(RSHRN_v, do_vec_shift_imm_narrow, a, rshrn_fns, 0) =20 +static WideShiftImmFn * const sqshrn_fns[] =3D { + gen_sqshrn_b, + gen_sqshrn_h, + gen_sqshrn_s, +}; +TRANS(SQSHRN_v, do_vec_shift_imm_narrow, a, sqshrn_fns, MO_SIGN) + +static WideShiftImmFn * const uqshrn_fns[] =3D { + gen_uqshrn_b, + gen_uqshrn_h, + gen_uqshrn_s, +}; +TRANS(UQSHRN_v, do_vec_shift_imm_narrow, a, uqshrn_fns, 0) + +static WideShiftImmFn * const sqshrun_fns[] =3D { + gen_sqshrun_b, + gen_sqshrun_h, + gen_sqshrun_s, +}; +TRANS(SQSHRUN_v, do_vec_shift_imm_narrow, a, sqshrun_fns, MO_SIGN) + +static WideShiftImmFn * const sqrshrn_fns[] =3D { + gen_sqrshrn_b, + gen_sqrshrn_h, + gen_sqrshrn_s, +}; +TRANS(SQRSHRN_v, do_vec_shift_imm_narrow, a, sqrshrn_fns, MO_SIGN) + +static WideShiftImmFn * const uqrshrn_fns[] =3D { + gen_uqrshrn_b, + gen_uqrshrn_h, + gen_uqrshrn_s, +}; +TRANS(UQRSHRN_v, do_vec_shift_imm_narrow, a, uqrshrn_fns, 0) + +static WideShiftImmFn * const sqrshrun_fns[] =3D { + gen_sqrshrun_b, + gen_sqrshrun_h, + gen_sqrshrun_s, +}; +TRANS(SQRSHRUN_v, do_vec_shift_imm_narrow, a, sqrshrun_fns, MO_SIGN) + /* * Advanced SIMD Scalar Shift by Immediate */ @@ -10514,20 +10672,6 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) } =20 switch (opcode) { - case 0x10: /* SHRN / SQSHRUN */ - case 0x11: /* RSHRN / SQRSHRUN */ - if (is_u) { - handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, - opcode, rn, rd); - } else { - unallocated_encoding(s); - } - break; - case 0x12: /* SQSHRN / UQSHRN */ - case 0x13: /* SQRSHRN / UQRSHRN */ - handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, - opcode, rn, rd); - break; case 0x1c: /* SCVTF / UCVTF */ handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, opcode, rn, rd); @@ -10544,6 +10688,10 @@ static void disas_simd_shift_imm(DisasContext *s, = uint32_t insn) case 0x0a: /* SHL / SLI */ case 0x0c: /* SQSHLU */ case 0x0e: /* SQSHL, UQSHL */ + case 0x10: /* SHRN / SQSHRUN */ + case 0x11: /* RSHRN / SQRSHRUN */ + case 0x12: /* SQSHRN / UQSHRN */ + case 0x13: /* SQRSHRN / UQRSHRN */ case 0x14: /* SSHLL / USHLL */ unallocated_encoding(s); return; diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 63e04ddfcd..042dc79d88 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1302,6 +1302,30 @@ SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..= ... @q_shli_h SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..... @q_shli_s SQSHLU_vi 0.10 11110 .... ... 01100 1 ..... ..... @q_shli_d =20 +SQSHRN_v 0.00 11110 .... ... 10010 1 ..... ..... @q_shri_b +SQSHRN_v 0.00 11110 .... ... 10010 1 ..... ..... @q_shri_h +SQSHRN_v 0.00 11110 .... ... 10010 1 ..... ..... @q_shri_s + +UQSHRN_v 0.10 11110 .... ... 10010 1 ..... ..... @q_shri_b +UQSHRN_v 0.10 11110 .... ... 10010 1 ..... ..... @q_shri_h +UQSHRN_v 0.10 11110 .... ... 10010 1 ..... ..... @q_shri_s + +SQSHRUN_v 0.10 11110 .... ... 10000 1 ..... ..... @q_shri_b +SQSHRUN_v 0.10 11110 .... ... 10000 1 ..... ..... @q_shri_h +SQSHRUN_v 0.10 11110 .... ... 10000 1 ..... ..... @q_shri_s + +SQRSHRN_v 0.00 11110 .... ... 10011 1 ..... ..... @q_shri_b +SQRSHRN_v 0.00 11110 .... ... 10011 1 ..... ..... @q_shri_h +SQRSHRN_v 0.00 11110 .... ... 10011 1 ..... ..... @q_shri_s + +UQRSHRN_v 0.10 11110 .... ... 10011 1 ..... ..... @q_shri_b +UQRSHRN_v 0.10 11110 .... ... 10011 1 ..... ..... @q_shri_h +UQRSHRN_v 0.10 11110 .... ... 10011 1 ..... ..... @q_shri_s + +SQRSHRUN_v 0.10 11110 .... ... 10001 1 ..... ..... @q_shri_b +SQRSHRUN_v 0.10 11110 .... ... 10001 1 ..... ..... @q_shri_h +SQRSHRUN_v 0.10 11110 .... ... 10001 1 ..... ..... @q_shri_s + # Advanced SIMD scalar shift by immediate =20 @shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ --=20 2.43.0 From nobody Thu Nov 14 04:02:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726109167646116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 160 +++++++-------------------------- target/arm/tcg/a64.decode | 30 +++++++ 2 files changed, 63 insertions(+), 127 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e6290e1145..071b6349fc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7456,6 +7456,35 @@ TRANS(SQSHL_si, do_scalar_shift_imm, a, f_scalar_sqs= hli[a->esz], false, 0) TRANS(UQSHL_si, do_scalar_shift_imm, a, f_scalar_uqshli[a->esz], false, 0) TRANS(SQSHLU_si, do_scalar_shift_imm, a, f_scalar_sqshlui[a->esz], false, = 0) =20 +static bool do_scalar_shift_imm_narrow(DisasContext *s, arg_rri_e *a, + WideShiftImmFn * const fns[3], + MemOp sign, bool zext) +{ + MemOp esz =3D a->esz; + + tcg_debug_assert(esz >=3D MO_8 && esz <=3D MO_32); + + if (fp_access_check(s)) { + TCGv_i64 rd =3D tcg_temp_new_i64(); + TCGv_i64 rn =3D tcg_temp_new_i64(); + + read_vec_element(s, rn, a->rn, 0, (esz + 1) | sign); + fns[esz](rd, rn, a->imm); + if (zext) { + tcg_gen_ext_i64(rd, rd, esz); + } + write_fp_dreg(s, a->rd, rd); + } + return true; +} + +TRANS(SQSHRN_si, do_scalar_shift_imm_narrow, a, sqshrn_fns, MO_SIGN, true) +TRANS(SQRSHRN_si, do_scalar_shift_imm_narrow, a, sqrshrn_fns, MO_SIGN, tru= e) +TRANS(UQSHRN_si, do_scalar_shift_imm_narrow, a, uqshrn_fns, 0, false) +TRANS(UQRSHRN_si, do_scalar_shift_imm_narrow, a, uqrshrn_fns, 0, false) +TRANS(SQSHRUN_si, do_scalar_shift_imm_narrow, a, sqshrun_fns, MO_SIGN, fal= se) +TRANS(SQRSHRUN_si, do_scalar_shift_imm_narrow, a, sqrshrun_fns, MO_SIGN, f= alse) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -9635,119 +9664,6 @@ static void disas_data_proc_fp(DisasContext *s, uin= t32_t insn) } } =20 -/* - * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) - * - * This code is handles the common shifting code and is used by both - * the vector and scalar code. - */ -static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, - bool round, bool accumulate, - bool is_u, int size, int shift) -{ - if (!round) { - if (is_u) { - gen_ushr_d(tcg_src, tcg_src, shift); - } else { - gen_sshr_d(tcg_src, tcg_src, shift); - } - } else if (size =3D=3D MO_64) { - if (is_u) { - gen_urshr_d(tcg_src, tcg_src, shift); - } else { - gen_srshr_d(tcg_src, tcg_src, shift); - } - } else { - if (is_u) { - gen_urshr_bhs(tcg_src, tcg_src, shift); - } else { - gen_srshr_bhs(tcg_src, tcg_src, shift); - } - } - - if (accumulate) { - tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); - } else { - tcg_gen_mov_i64(tcg_res, tcg_src); - } -} - -/* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with - * (signed/unsigned) narrowing */ -static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool i= s_q, - bool is_u_shift, bool is_u_narrow, - int immh, int immb, int opcode, - int rn, int rd) -{ - int immhb =3D immh << 3 | immb; - int size =3D 32 - clz32(immh) - 1; - int esize =3D 8 << size; - int shift =3D (2 * esize) - immhb; - int elements =3D is_scalar ? 1 : (64 / esize); - bool round =3D extract32(opcode, 0, 1); - MemOp ldop =3D (size + 1) | (is_u_shift ? 0 : MO_SIGN); - TCGv_i64 tcg_rn, tcg_rd, tcg_final; - - static NeonGenOne64OpEnvFn * const signed_narrow_fns[4][2] =3D { - { gen_helper_neon_narrow_sat_s8, - gen_helper_neon_unarrow_sat8 }, - { gen_helper_neon_narrow_sat_s16, - gen_helper_neon_unarrow_sat16 }, - { gen_helper_neon_narrow_sat_s32, - gen_helper_neon_unarrow_sat32 }, - { NULL, NULL }, - }; - static NeonGenOne64OpEnvFn * const unsigned_narrow_fns[4] =3D { - gen_helper_neon_narrow_sat_u8, - gen_helper_neon_narrow_sat_u16, - gen_helper_neon_narrow_sat_u32, - NULL - }; - NeonGenOne64OpEnvFn *narrowfn; - - int i; - - assert(size < 4); - - if (extract32(immh, 3, 1)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - if (is_u_shift) { - narrowfn =3D unsigned_narrow_fns[size]; - } else { - narrowfn =3D signed_narrow_fns[size][is_u_narrow ? 1 : 0]; - } - - tcg_rn =3D tcg_temp_new_i64(); - tcg_rd =3D tcg_temp_new_i64(); - tcg_final =3D tcg_temp_new_i64(); - - for (i =3D 0; i < elements; i++) { - read_vec_element(s, tcg_rn, rn, i, ldop); - handle_shri_with_rndacc(tcg_rd, tcg_rn, round, - false, is_u_shift, size+1, shift); - narrowfn(tcg_rd, tcg_env, tcg_rd); - if (i =3D=3D 0) { - tcg_gen_extract_i64(tcg_final, tcg_rd, 0, esize); - } else { - tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, e= size); - } - } - - if (!is_q) { - write_vec_element(s, tcg_final, rd, 0, MO_64); - } else { - write_vec_element(s, tcg_final, rd, 1, MO_64); - } - clear_vec_high(s, is_q, rd); -} - /* Common vector code for handling integer to FP conversion */ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, int elements, int is_signed, @@ -10013,20 +9929,6 @@ static void disas_simd_scalar_shift_imm(DisasContex= t *s, uint32_t insn) handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, opcode, rn, rd); break; - case 0x10: /* SQSHRUN, SQSHRUN2 */ - case 0x11: /* SQRSHRUN, SQRSHRUN2 */ - if (!is_u) { - unallocated_encoding(s); - return; - } - handle_vec_simd_sqshrn(s, true, false, false, true, - immh, immb, opcode, rn, rd); - break; - case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ - case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ - handle_vec_simd_sqshrn(s, true, false, is_u, is_u, - immh, immb, opcode, rn, rd); - break; case 0x1f: /* FCVTZS, FCVTZU */ handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn,= rd); break; @@ -10039,6 +9941,10 @@ static void disas_simd_scalar_shift_imm(DisasContex= t *s, uint32_t insn) case 0x0a: /* SHL / SLI */ case 0x0c: /* SQSHLU */ case 0x0e: /* SQSHL, UQSHL */ + case 0x10: /* SQSHRUN */ + case 0x11: /* SQRSHRUN */ + case 0x12: /* SQSHRN, UQSHRN */ + case 0x13: /* SQRSHRN, UQRSHRN */ unallocated_encoding(s); break; } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 042dc79d88..331a8e180c 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1328,6 +1328,12 @@ SQRSHRUN_v 0.10 11110 .... ... 10001 1 ..... ..= ... @q_shri_s =20 # Advanced SIMD scalar shift by immediate =20 +@shri_b .... ..... 0001 ... ..... . rn:5 rd:5 \ + &rri_e esz=3D0 imm=3D%neon_rshift_i3 +@shri_h .... ..... 001 .... ..... . rn:5 rd:5 \ + &rri_e esz=3D1 imm=3D%neon_rshift_i4 +@shri_s .... ..... 01 ..... ..... . rn:5 rd:5 \ + &rri_e esz=3D2 imm=3D%neon_rshift_i5 @shri_d .... ..... 1 ...... ..... . rn:5 rd:5 \ &rri_e esz=3D3 imm=3D%neon_rshift_i6 =20 @@ -1363,3 +1369,27 @@ SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..= ... @shli_b SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_h SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_s SQSHLU_si 0111 11110 .... ... 01100 1 ..... ..... @shli_d + +SQSHRN_si 0101 11110 .... ... 10010 1 ..... ..... @shri_b +SQSHRN_si 0101 11110 .... ... 10010 1 ..... ..... @shri_h +SQSHRN_si 0101 11110 .... ... 10010 1 ..... ..... @shri_s + +UQSHRN_si 0111 11110 .... ... 10010 1 ..... ..... @shri_b +UQSHRN_si 0111 11110 .... ... 10010 1 ..... ..... @shri_h +UQSHRN_si 0111 11110 .... ... 10010 1 ..... ..... @shri_s + +SQSHRUN_si 0111 11110 .... ... 10000 1 ..... ..... @shri_b +SQSHRUN_si 0111 11110 .... ... 10000 1 ..... ..... @shri_h +SQSHRUN_si 0111 11110 .... ... 10000 1 ..... ..... @shri_s + +SQRSHRN_si 0101 11110 .... ... 10011 1 ..... ..... @shri_b +SQRSHRN_si 0101 11110 .... ... 10011 1 ..... ..... @shri_h +SQRSHRN_si 0101 11110 .... ... 10011 1 ..... ..... @shri_s + +UQRSHRN_si 0111 11110 .... ... 10011 1 ..... ..... @shri_b +UQRSHRN_si 0111 11110 .... ... 10011 1 ..... ..... @shri_h +UQRSHRN_si 0111 11110 .... ... 10011 1 ..... ..... @shri_s + +SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_b +SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_h +SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_s --=20 2.43.0