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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fe4e7esm3186947b3a.80.2024.09.11.09.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 09:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1726073454; x=1726678254; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9crvsERH/myYSJkgKez5YbnhkNv578itQ81kZkhssYk=; b=Z3H0ie0Y/5S2XO/J2tqaomsBf9dDnAdkGTuhd8BBhvA51efiSADVVg+0ip34Z8y6al PNJQJoovdhurwRNTLzaOwKS+9Ns1CBATROdIBoI2LbcrewgeXzKp9XWLPPnxIVqf7EcK ghge81Xv7VqTtm0FkolJNanPYEQdmEgXqs+AcXj38VXhux7zxs5OgZRdEIQeDKLX2/TP jpqGDpQn4vIEJQI8ynijQgN4+BZ9hlaWm17tBrQD1W60BXAPzzN/T8F5JjpEJNtwOBbj OMDki8T4xb0ZsNCqjnm8Nbcw3kCuKtqXB6a78wuRZQRH20AqKO3eUK9StTKbcMgqTn2I oTog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726073454; x=1726678254; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9crvsERH/myYSJkgKez5YbnhkNv578itQ81kZkhssYk=; b=m7/AWcmOiGsCsyIVa2D29M+jVU+vB4XtV8tLgSFbiEse4uvYdZ8g54p0moBnq2pEA7 UJCtKIDkKPqcQc4qjBriF3eynANVbO5eBc8i/8a6aGliLSqvIQDXbuf1xvqLTQxy2eHe EFWZ+pBUDdAspayzp3ugjxHurKKlTjpRSixKs8C2FkhgjbTkrOPUiPAGKXprHaOW0P0a 8j7N9XXicm6OT4H2Mf5KFFdgSBYRrJgHEkDc+d2XucipOlzLHbGfvY9HHDIIuNyKb097 tFDbbtF/pT28UoYlqnbjYnyYgvU9se1y4LRPpxVa6fOMk4DXJZdc//Tkfa+IXi+83RSE I++g== X-Gm-Message-State: AOJu0YxrkkJtR44rKw8/3cgYYubQQTp7+GRN1Q9x/8ddtI3gpKGW1pDO 2AANCzg+A50/Hq/EYC9JU56/HXpP3jjnUkm6JwKcDOKrw0VRMI7DO6FOT8tbzbRIY7hr6lLJ+ly J X-Google-Smtp-Source: AGHT+IGu+J62BcE1uGscyzU1511se5adC1H8xAkhtv3svJuPWSPxr10+fvKM+UCnUBaGX1mnx4RgNA== X-Received: by 2002:a05:6a21:4a4c:b0:1c1:92f8:d3c6 with SMTP id adf61e73a8af0-1cf5e143e33mr7139906637.27.1726073453629; Wed, 11 Sep 2024 09:50:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: zhiwei_liu@linux.alibaba.com, tangtiancheng.ttc@alibaba-inc.com, philmd@linaro.org Subject: [PATCH v2 05/18] tcg/ppc: Do not expand cmp_vec early Date: Wed, 11 Sep 2024 09:50:34 -0700 Message-ID: <20240911165047.1035764-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911165047.1035764-1-richard.henderson@linaro.org> References: <20240911165047.1035764-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1726073618981116600 Content-Type: text/plain; charset="utf-8" Move expansion to opcode generation. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 169 +++++++++++++++++++++------------------ 1 file changed, 90 insertions(+), 79 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3553a47ba9..497e130581 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3567,12 +3567,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: return vece <=3D MO_32; - case INDEX_op_cmp_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: case INDEX_op_rotli_vec: return vece <=3D MO_32 || have_isa_2_07 ? -1 : 0; + case INDEX_op_cmp_vec: + return vece <=3D MO_32 || have_isa_2_07 ? 1 : 0; case INDEX_op_neg_vec: return vece >=3D MO_32 && have_isa_3_00; case INDEX_op_mul_vec: @@ -3713,6 +3714,90 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType = type, unsigned vece, return true; } =20 +static void tcg_out_not_vec(TCGContext *s, TCGReg a0, TCGReg a1) +{ + tcg_out32(s, VNOR | VRT(a0) | VRA(a1) | VRB(a1)); +} + +static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, + TCGReg a1, TCGReg a2, TCGCond cond) +{ + static const uint32_t + eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + ne_op[4] =3D { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, + gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, + gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }; + uint32_t insn; + + bool need_swap =3D false, need_inv =3D false; + + tcg_debug_assert(vece <=3D MO_32 || have_isa_2_07); + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + if (have_isa_3_00 && vece <=3D MO_32) { + break; + } + /* fall through */ + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv =3D true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap =3D true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap =3D need_inv =3D true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond =3D tcg_invert_cond(cond); + } + if (need_swap) { + TCGReg swap =3D a1; + a1 =3D a2; + a2 =3D swap; + cond =3D tcg_swap_cond(cond); + } + + switch (cond) { + case TCG_COND_EQ: + insn =3D eq_op[vece]; + break; + case TCG_COND_NE: + insn =3D ne_op[vece]; + break; + case TCG_COND_GT: + insn =3D gts_op[vece]; + break; + case TCG_COND_GTU: + insn =3D gtu_op[vece]; + break; + default: + g_assert_not_reached(); + } + tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); + + return need_inv; +} + +static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, + TCGReg a1, TCGReg a2, TCGCond cond) +{ + if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { + tcg_out_not_vec(s, a0, a0); + } +} + static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], @@ -3723,10 +3808,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, sub_op[4] =3D { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, mul_op[4] =3D { 0, 0, VMULUWM, VMULLD }, neg_op[4] =3D { 0, 0, VNEGW, VNEGD }, - eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, - ne_op[4] =3D { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, - gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, - gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, usadd_op[4] =3D { VADDUBS, VADDUHS, VADDUWS, 0 }, sssub_op[4] =3D { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, @@ -3820,9 +3901,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, insn =3D VANDC; break; case INDEX_op_not_vec: - insn =3D VNOR; - a2 =3D a1; - break; + tcg_out_not_vec(s, a0, a1); + return; case INDEX_op_orc_vec: insn =3D VORC; break; @@ -3837,23 +3917,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, break; =20 case INDEX_op_cmp_vec: - switch (args[3]) { - case TCG_COND_EQ: - insn =3D eq_op[vece]; - break; - case TCG_COND_NE: - insn =3D ne_op[vece]; - break; - case TCG_COND_GT: - insn =3D gts_op[vece]; - break; - case TCG_COND_GTU: - insn =3D gtu_op[vece]; - break; - default: - g_assert_not_reached(); - } - break; + tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); + return; =20 case INDEX_op_bitsel_vec: tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); @@ -3921,56 +3986,6 @@ static void expand_vec_shi(TCGType type, unsigned ve= ce, TCGv_vec v0, tcgv_vec_arg(v1), tcgv_vec_arg(t1)); } =20 -static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) -{ - bool need_swap =3D false, need_inv =3D false; - - tcg_debug_assert(vece <=3D MO_32 || have_isa_2_07); - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_GT: - case TCG_COND_GTU: - break; - case TCG_COND_NE: - if (have_isa_3_00 && vece <=3D MO_32) { - break; - } - /* fall through */ - case TCG_COND_LE: - case TCG_COND_LEU: - need_inv =3D true; - break; - case TCG_COND_LT: - case TCG_COND_LTU: - need_swap =3D true; - break; - case TCG_COND_GE: - case TCG_COND_GEU: - need_swap =3D need_inv =3D true; - break; - default: - g_assert_not_reached(); - } - - if (need_inv) { - cond =3D tcg_invert_cond(cond); - } - if (need_swap) { - TCGv_vec t1; - t1 =3D v1, v1 =3D v2, v2 =3D t1; - cond =3D tcg_swap_cond(cond); - } - - vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); - - if (need_inv) { - tcg_gen_not_vec(vece, v0, v0); - } -} - static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) { @@ -4045,10 +4060,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, case INDEX_op_rotli_vec: expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); break; - case INDEX_op_cmp_vec: - v2 =3D temp_tcgv_vec(arg_temp(a2)); - expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); - break; case INDEX_op_mul_vec: v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_mul(type, vece, v0, v1, v2); --=20 2.43.0