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Wed, 11 Sep 2024 21:31:42 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1726064792; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=8f6YkZ+ioz+svRX9lekPFU3pDZ9Dr096ApWa98Nt/fg=; b=DuMqi0RM2+EodaGdhUMFfXbfDlV3jo4T5G3CgOa84BvhqgH3+tLeeG46G6bzMYSYBZizB7FUgDv/HFF3PVGXh1t2rZPaFKUQDHeDis6/aMvhZZymHX/WdpUz9C5Lk4eKGbSfXyEKCKZAYvzVl7IG/fktlM5dzG2nErmhnDfGVT4= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v4 08/12] tcg/riscv: Implement vector sat/mul ops Date: Wed, 11 Sep 2024 21:26:26 +0800 Message-Id: <20240911132630.461-9-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240911132630.461-1-zhiwei_liu@linux.alibaba.com> References: <20240911132630.461-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 36 ++++++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index cf86f3729c..0a091c12d2 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -281,6 +281,12 @@ typedef enum { OPC_VXOR_VI =3D 0x2c000057 | V_OPIVI, =20 OPC_VRSUB_VI =3D 0xc000057 | V_OPIVI, + OPC_VMUL_VV =3D 0x94000057 | V_OPMVV, + OPC_VSADD_VV =3D 0x84000057 | V_OPIVV, + OPC_VSSUB_VV =3D 0x8c000057 | V_OPIVV, + OPC_VSADDU_VV =3D 0x80000057 | V_OPIVV, + OPC_VSSUBU_VV =3D 0x88000057 | V_OPIVV, + OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, @@ -2390,6 +2396,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, set_vtype_len_sew(s, type, vece); tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0, true); break; + case INDEX_op_mul_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2, true); + break; + case INDEX_op_ssadd_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSADD_VV, a0, a1, a2, true); + break; + case INDEX_op_sssub_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSSUB_VV, a0, a1, a2, true); + break; + case INDEX_op_usadd_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSADDU_VV, a0, a1, a2, true); + break; + case INDEX_op_ussub_vec: + set_vtype_len_sew(s, type, vece); + tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); + break; case INDEX_op_cmpsel_vec: tcg_out_cmpsel(s, type, vece, args[5], a0, a1, a2, const_args[2], args[3], const_args[3], args[4], const_args[4]); @@ -2434,6 +2460,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_xor_vec: case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: case INDEX_op_cmpsel_vec: return 1; case INDEX_op_cmp_vec: @@ -2596,6 +2627,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return C_O1_I2(v, v, v); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ae10381e02..1d4d8878ce 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -160,8 +160,8 @@ typedef enum { #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 1 --=20 2.43.0