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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc84efsm25431b3a.8.2024.09.09.11.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 11:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1725905236; x=1726510036; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bKKi0pMicJbraFe0EvfP4hRpwt+nXYvkFQlWAnrDKc0=; b=akUttigd8EVsy6ByCyyfjFGudFoXT+6d3PaKCWyr/tLitlyHohOacXZX653VF2J7pW QqROtvbidu14tmj4wxCuX8ToybH5xhRnfuheCJlEfQbuxD1kLT+GnVxJFlu5OKwcN4wN aAUPh4NwUYWmt0GZ7l98+/DG2ckFqGDgop3TfG806PCOP2AWV9S0fo3u/B3ECESRwsEP URIsYyXwofz3NLYMgr3nq0ty/7/in3ya9QGdOQVSQmpVa+sHZdIlrf8zAuX4vOJ3p/vT rlyjtFqlEuijTFbNXyJiMzCAdyfoPRnqAxGHuXVYJ5eD2a5JSrXwEW511YzGj2IROOFM 57KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725905236; x=1726510036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bKKi0pMicJbraFe0EvfP4hRpwt+nXYvkFQlWAnrDKc0=; b=WVmKHRNc7LNYbNtgVM3hMGrYtBhLaj4JO3XKuNfk+2W+fKZla+mtHyLv4gOE9P7Scs HUhCxfnF2fB3JjWSSyGOlzNSDmdhEaLD+4jRgyTYMqjiM/sTnS8NcTygntVG31KhA1Jy QPS2QyfcL1ycLX4VkqiKXx10rUX0iUxf7HAwB7u4Dm/F/edPaXuXqGCXaEa3kcoXYPTr b8VaOLrmHxwK3ZRziKMfJ/2JHMiBNUa0Qk9SbTV0NU4Tzq2JK+fufESQvjpgXsQMLZA5 Hn5s+dZMH+aw+OKuah7gRRJFfeMHj98v1Ov2e5bNHacPlwSPMcUd1Y3tSR+wKz8lbCrU 16Pw== X-Gm-Message-State: AOJu0Ywdk2dUfWE/tEUMlW3EoMYgeu9yMEBPVXTwhhNzjYH4qssYOYrx PxHOYpXJbvShKywGWZ/GewyNPeN2zJyoGIsvyApEkSSXcxNXwMt59HjRKT1C2UjLJwobesWUmmf d X-Google-Smtp-Source: AGHT+IFsVeeZiS/sawRrbLTH9LqJb/j426q/xV7fUshPpfqBz8Bt2U0zif9hrBV6p6uw6sunm86Hng== X-Received: by 2002:a05:6a21:4d81:b0:1cf:43c6:d53f with SMTP id adf61e73a8af0-1cf43c6d637mr3376136637.19.1725905235888; Mon, 09 Sep 2024 11:07:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, chauser@pullman.com Subject: [PATCH v4 2/5] target/sparc: Populate sparc32 FQ when raising fp exception Date: Mon, 9 Sep 2024 11:07:09 -0700 Message-ID: <20240909180712.651651-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240909180712.651651-1-richard.henderson@linaro.org> References: <20240909180712.651651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1725905266689116600 Content-Type: text/plain; charset="utf-8" From: Carl Hauser Implement a single instruction floating point queue, populated while delivering an fp exception. Signed-off-by: Carl Hauser [rth: Split from a larger patch] Signed-off-by: Richard Henderson --- target/sparc/int32_helper.c | 40 +++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 6b7d65b031..f2dd8bcb2e 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -21,10 +21,10 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "sysemu/runstate.h" =20 - static const char * const excp_names[0x80] =3D { [TT_TFAULT] =3D "Instruction Access Fault", [TT_ILL_INSN] =3D "Illegal Instruction", @@ -116,22 +116,9 @@ void sparc_cpu_do_interrupt(CPUState *cs) =20 qemu_log("%6d: %s (v=3D%02x)\n", count, name, intno); log_cpu_state(cs, 0); -#if 0 - { - int i; - uint8_t *ptr; - - qemu_log(" code=3D"); - ptr =3D (uint8_t *)env->pc; - for (i =3D 0; i < 16; i++) { - qemu_log(" %02x", ldub(ptr + i)); - } - qemu_log("\n"); - } -#endif count++; } -#if !defined(CONFIG_USER_ONLY) +#ifndef CONFIG_USER_ONLY if (env->psret =3D=3D 0) { if (cs->exception_index =3D=3D 0x80 && env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { @@ -143,6 +130,29 @@ void sparc_cpu_do_interrupt(CPUState *cs) } return; } + if (intno =3D=3D TT_FP_EXCP) { + /* + * The sparc32 fpu has three states related to exception handling. + * The FPop that signals an exception transitions from fp_execute + * to fp_exception_pending. A subsequent FPop transitions from + * fp_exception_pending to fp_exception, which forces the trap. + * + * If the queue is not empty, this trap is due to execution of an + * illegal FPop while in fp_exception state. Here we are to + * re-enter fp_exception_pending state without queuing the insn. + * + * We do not model the fp_exception_pending state, but instead + * skip directly to fp_exception state. We advance pc/npc to + * mimic delayed trap delivery as if by the subsequent insn. + */ + if (!env->fsr_qne) { + env->fsr_qne =3D FSR_QNE; + env->fq.s.addr =3D env->pc; + env->fq.s.insn =3D cpu_ldl_code(env, env->pc); + } + env->pc =3D env->npc; + env->npc =3D env->npc + 4; + } #endif env->psret =3D 0; cwp =3D cpu_cwp_dec(env, env->cwp - 1); --=20 2.43.0