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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37895675b8bsm5413517f8f.54.2024.09.09.01.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 01:32:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1725870764; x=1726475564; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=qaZQYz0SvX+ateb02T1sX7QlYRxIfBB8EH9iwlM8BWE=; b=cGzvVR05YunBOVkWL8BBXvGQjnaYt0O5+hTtW6VEAVWGlB4AEsV/UtD24ld4Uw0MBr H6gTzBUpUsBKVw036+qM7j3h7ONiuGfVP5dpP8KmwxA75Lp84LKj+8cm4tCEOpTm5yR9 XciXsJxwAujt2QdHlb4p+mqbxmucTNW/AYaZopCKmVs03jFXkjSuEY0WQi8FARA08U+I AZp672nR1Zo9TqZ8iovSSvwN2ZeKIBl+3dPsI9EpeaxpEmq6yHoJL1TNoAHtDBvg/D4r VdkuAGLbVh9nP5Ithgfti9jklR+0wHw/1ZrQGcc61O8rM3uCejvCBLsCvm7fJYlQnq7q Ce2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725870764; x=1726475564; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qaZQYz0SvX+ateb02T1sX7QlYRxIfBB8EH9iwlM8BWE=; b=L/FP8XNvSTNROvKQsjEzWqo2foWq35yYImCxhxEsiAR/2I4C585ghcYjLJAVWSWrtx jWdZAH628Bp6OlqgkASV+o1qAuOw195bjOHQ7s197LrqZ/gN/MnbTm2gJSzr8DRUWSg+ RwxksEhN/zW8XuA5GLkF/ben1C3Jc7QhgbvLkIpy6pUmZngHxGo2ijAsPWJ+4DnflrFO UbxEM1U5j40Fc0vI8QccYhwTkmr2SUKrHl7fNyynrEbikS9+BasiOOIgkwXBioUZFVJc 9uSwVoypcrvuaZf5h7NcW2zBZb3mhEyb8QtneGjx84Pnsw0Nas1lcJx2zmq98qtUZBnN CzUQ== X-Forwarded-Encrypted: i=1; AJvYcCU5pTahVUOn9NiqHHqzo1apTTqZvrs0K5eaBpWfVYVd0YAKrE8MEdWL+lC6vcz8hH7cQZo17WFlnFs4@nongnu.org X-Gm-Message-State: AOJu0Yw5Nd+jIiKaHyCxdwryDg873IOFzhJlaulUnxpZ7tgU9QfP9/nD GAY9uf1E2eBalBY90v47hqt77FGQ79KFkQLSbmXU9n3zfKiY5wslQgUrhTPiTm0= X-Google-Smtp-Source: AGHT+IEA1cN72rSRhwl/iZZZqgVhUKgbjBg9EjiAhQbZH1jrWALTHPiukfU1ftJN22vbx6ApTh+4fA== X-Received: by 2002:adf:ea0e:0:b0:374:c05f:2313 with SMTP id ffacd0b85a97d-3789243fa0bmr5826589f8f.45.1725870763618; Mon, 09 Sep 2024 01:32:43 -0700 (PDT) From: Andrew Jones To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, zong.li@sifive.com, liwei1518@gmail.com, cwshu@andestech.com, dbarboza@ventanamicro.com, richard.henderson@linaro.org, philmd@linaro.org Subject: [PATCH v2] target/riscv32: Fix masking of physical address Date: Mon, 9 Sep 2024 10:32:42 +0200 Message-ID: <20240909083241.43836-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1725870837925116600 Content-Type: text/plain; charset="utf-8" C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32 bits of the u64 being zero. If that result is then used as a mask on another u64 the upper 32 bits will be cleared. rv32 physical addresses may be up to 34 bits wide, so we don't want to clear the high bits while page aligning the address. The fix is to use hwaddr for the mask, which, even on rv32, is 64-bits wide. Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP= entries.") Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- -v2: Switch from signed long to hwaddr target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 395a1d914061..4b2c72780c36 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1323,7 +1323,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, int ret =3D TRANSLATE_FAIL; int mode =3D mmuidx_priv(mmu_idx); /* default TLB page size */ - target_ulong tlb_size =3D TARGET_PAGE_SIZE; + hwaddr tlb_size =3D TARGET_PAGE_SIZE; =20 env->guest_phys_fault_addr =3D 0; =20 @@ -1375,7 +1375,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 qemu_log_mask(CPU_LOG_MMU, "%s PMP address=3D" HWADDR_FMT_plx " ret %d = prot" - " %d tlb_size " TARGET_FMT_lu "\n", + " %d tlb_size %" HWADDR_PRIu "\n", __func__, pa, ret, prot_pmp, tlb_size); =20 prot &=3D prot_pmp; @@ -1409,7 +1409,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 qemu_log_mask(CPU_LOG_MMU, "%s PMP address=3D" HWADDR_FMT_plx " ret %d prot" - " %d tlb_size " TARGET_FMT_lu "\n", + " %d tlb_size %" HWADDR_PRIu "\n", __func__, pa, ret, prot_pmp, tlb_size); =20 prot &=3D prot_pmp; --=20 2.46.0