From nobody Sun Nov 24 08:27:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1725799480; cv=none; d=zohomail.com; s=zohoarc; b=GKLIwKq0fNMrx5dYCZbLQPOeLUi0VupXtIw2IQYjKCz6eIBohLtrX/6KxcWoE0HKhdf6yquKA23GS+GdIsDd2iIHrRpXSzCRF77IRX/aG5oEbcCp8ruyj/iUP0EgqlgM6Vpfnt9lihxBVsA1AJ/v02DN95Jl+d340SgKm6Bfebg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1725799480; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1OkcmAi7PdcGK3Hewbz3hC8uV56w7yyw/amah65vXpM=; b=Vc/vlVadot5CMh/tTqHdfQItV2a205PnKtcXGoPqm1gGNj26kJeySi4jfkxCnSZRULsRpd32D3inRuQbS4zPVbaLvU2OyLdivyoC7O6UIvh4RK0T+qHXRtJJYRl8HmMyZTXC9xKMjYGQc6ZSNMMDj7fvZWzOpqwZiEVmC+30jRs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1725799480705917.5711202376616; Sun, 8 Sep 2024 05:44:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1snHGl-0008EV-NI; Sun, 08 Sep 2024 08:43:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1snHGd-0007nm-Bd; Sun, 08 Sep 2024 08:43:47 -0400 Received: from mgamail.intel.com ([198.175.65.15]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1snHGa-0006B4-Qz; Sun, 08 Sep 2024 08:43:47 -0400 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2024 05:43:44 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa001.fm.intel.com with ESMTP; 08 Sep 2024 05:43:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725799425; x=1757335425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BvJHpJ3VnH6FTy0YX6zsYzLEo6pd3YTqpGtex2MXUQQ=; b=MYR3OZnWB1bIKuOc4YE9PMYX7HQ93F9uNlPjoMF5/P/bwOYQhglCZhsu Qkav2vPy2ZtiAyP35DeLIWK70GoUufSVtjEmFd/D/g2SxX5pE/xFv3mau NEclRMIEPZCWM3hQRBCcS1cPuRJWqBZklqWQFJqiMOl4Y1J63OQkh7iqe rXgguzW/m5/VkiJUtPaFOPMx8QC9wzV5EFr2k1wcN06iMCRKLC7L1UKRJ 6AuUHpptmVdHq5UHNQ78zFRPnBa9gZvFApKHNlw5oGscaFkpDaY0Umsak 5gMBewFLM0gOakUPLzC1Fj5cHRI/rGecjXnho8EqySNRJhFa7mNBEuE88 Q==; X-CSE-ConnectionGUID: sE9vRaPzQ025amymSHaz1A== X-CSE-MsgGUID: 2Om3g5DzT1mI6wNGiI9q2Q== X-IronPort-AV: E=McAfee;i="6700,10204,11189"; a="28238167" X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="28238167" X-CSE-ConnectionGUID: ae3sS5fNRvCsQBpoVcUQAQ== X-CSE-MsgGUID: IwRKVVKtQM+aR2pi0qKjlQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,212,1719903600"; d="scan'208";a="97196546" From: Zhao Liu To: =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng , Alireza Sanaee Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v2 3/7] hw/core: Add smp cache topology for machine Date: Sun, 8 Sep 2024 20:59:16 +0800 Message-Id: <20240908125920.1160236-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240908125920.1160236-1-zhao1.liu@intel.com> References: <20240908125920.1160236-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1725799482417116600 Content-Type: text/plain; charset="utf-8" With smp-cache object support, add smp cache topology for machine by linking the smp-cache object. Also add a helper to access cache topology level. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- Changes since Patch v1: * Integrated cache properties list into MachineState and used -machine to configure SMP cache properties. (Markus) Changes since RFC v2: * Linked machine's smp_cache to smp-cache object instead of a builtin structure. This is to get around the fact that the keyval format of -machine can't support JSON. * Wrapped the cache topology level access into a helper. --- hw/core/machine-smp.c | 41 ++++++++++++++++++++++++++++++++++++++++ hw/core/machine.c | 44 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 10 ++++++++++ 3 files changed, 95 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 5d8d7edcbd3f..b517c3471d1a 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -261,6 +261,41 @@ void machine_parse_smp_config(MachineState *ms, } } =20 +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp) +{ + const SmpCachePropertiesList *node; + DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); + + for (node =3D caches; node; node =3D node->next) { + /* Prohibit users from setting the cache topology level to invalid= . */ + if (node->value->topology =3D=3D CPU_TOPOLOGY_LEVEL_INVALID) { + error_setg(errp, + "Invalid cache topology level: %s. " + "The topology should match the " + "valid CPU topology level", + CpuTopologyLevel_str(node->value->topology)); + return false; + } + + /* Prohibit users from repeating settings. */ + if (test_bit(node->value->cache, caches_bitmap)) { + error_setg(errp, + "Invalid cache properties: %s. " + "The cache properties are duplicated", + CacheLevelAndType_str(node->value->cache)); + return false; + } else { + ms->smp_cache.props[node->value->cache].topology =3D + node->value->topology; + set_bit(node->value->cache, caches_bitmap); + } + } + + return true; +} + unsigned int machine_topo_get_cores_per_socket(const MachineState *ms) { return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.di= es; @@ -270,3 +305,9 @@ unsigned int machine_topo_get_threads_per_socket(const = MachineState *ms) { return ms->smp.threads * machine_topo_get_cores_per_socket(ms); } + +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + CacheLevelAndType cache) +{ + return ms->smp_cache.props[cache].topology; +} diff --git a/hw/core/machine.c b/hw/core/machine.c index adaba17ebac1..518beb9f883a 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -932,6 +932,40 @@ static void machine_set_smp(Object *obj, Visitor *v, c= onst char *name, machine_parse_smp_config(ms, config, errp); } =20 +static void machine_get_smp_cache(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + SmpCache *cache =3D &ms->smp_cache; + SmpCachePropertiesList *head =3D NULL; + SmpCachePropertiesList **tail =3D &head; + + for (int i =3D 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + SmpCacheProperties *node =3D g_new(SmpCacheProperties, 1); + + node->cache =3D cache->props[i].cache; + node->topology =3D cache->props[i].topology; + QAPI_LIST_APPEND(tail, node); + } + + visit_type_SmpCachePropertiesList(v, name, &head, errp); + qapi_free_SmpCachePropertiesList(head); +} + +static void machine_set_smp_cache(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + SmpCachePropertiesList *caches; + + if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { + return; + } + + machine_parse_smp_cache(ms, caches, errp); + qapi_free_SmpCachePropertiesList(caches); +} + static void machine_get_boot(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1057,6 +1091,11 @@ static void machine_class_init(ObjectClass *oc, void= *data) object_class_property_set_description(oc, "smp", "CPU topology"); =20 + object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", + machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); + object_class_property_set_description(oc, "smp-cache", + "Cache properties list for SMP machine"); + object_class_property_add(oc, "phandle-start", "int", machine_get_phandle_start, machine_set_phandle_start, NULL, NULL); @@ -1195,6 +1234,11 @@ static void machine_initfn(Object *obj) ms->smp.cores =3D 1; ms->smp.threads =3D 1; =20 + for (int i =3D 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + ms->smp_cache.props[i].cache =3D (CacheLevelAndType)i; + ms->smp_cache.props[i].topology =3D CPU_TOPOLOGY_LEVEL_DEFAULT; + } + machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index 9a492770cbb9..64439dc7da2c 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -43,8 +43,13 @@ void machine_set_cpu_numa_node(MachineState *machine, Error **errp); void machine_parse_smp_config(MachineState *ms, const SMPConfiguration *config, Error **errp= ); +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp); unsigned int machine_topo_get_cores_per_socket(const MachineState *ms); unsigned int machine_topo_get_threads_per_socket(const MachineState *ms); +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + CacheLevelAndType cache); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t s= ize); =20 /** @@ -363,6 +368,10 @@ typedef struct CpuTopology { unsigned int max_cpus; } CpuTopology; =20 +typedef struct SmpCache { + SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX]; +} SmpCache; + /** * MachineState: */ @@ -413,6 +422,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + SmpCache smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; --=20 2.34.1