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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=satur9nine@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1725745627281116600 Content-Type: text/plain; charset="utf-8" These changes allow the official STM32L4xx HAL UART driver to function properly with the b-l475e-iot01a machine. Modifying USART_CR1 TE bit should alter USART_ISR TEACK bit, and likewise for RE and REACK bit. USART registers may be accessed via 16-bit instructions. Reseting USART_CR1 UE bit should restore ISR to default value. Fixes: 87b77e6e01ca ("hw/char/stm32l4x5_usart: Enable serial read and write= ") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540 Signed-off-by: Jacob Abrams --- Changes since version 1: - Add qtest_quit to end of new test hw/char/stm32l4x5_usart.c | 29 ++++++++++++++++++--- tests/qtest/stm32l4x5_usart-test.c | 41 +++++++++++++++++++++++++++++- 2 files changed, 66 insertions(+), 4 deletions(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index fc5dcac0c4..859fc6236a 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -154,6 +154,28 @@ REG32(RDR, 0x24) REG32(TDR, 0x28) FIELD(TDR, TDR, 0, 9) =20 +#define ISR_RESET_VALUE (0x020000C0) + +static void stm32l4x5_update_isr(Stm32l4x5UsartBaseState *s) +{ + if (!(s->cr1 & R_CR1_UE_MASK)) { + s->isr =3D ISR_RESET_VALUE; + return; + } + + if (s->cr1 & R_CR1_TE_MASK) { + s->isr |=3D R_ISR_TEACK_MASK; + } else { + s->isr &=3D ~R_ISR_TEACK_MASK; + } + + if (s->cr1 & R_CR1_RE_MASK) { + s->isr |=3D R_ISR_REACK_MASK; + } else { + s->isr &=3D ~R_ISR_REACK_MASK; + } +} + static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) { if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) = || @@ -367,7 +389,7 @@ static void stm32l4x5_usart_base_reset_hold(Object *obj= , ResetType type) s->brr =3D 0x00000000; s->gtpr =3D 0x00000000; s->rtor =3D 0x00000000; - s->isr =3D 0x020000C0; + s->isr =3D ISR_RESET_VALUE; s->rdr =3D 0x00000000; s->tdr =3D 0x00000000; =20 @@ -456,6 +478,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hw= addr addr, case A_CR1: s->cr1 =3D value; stm32l4x5_update_params(s); + stm32l4x5_update_isr(s); stm32l4x5_update_irq(s); return; case A_CR2: @@ -508,12 +531,12 @@ static const MemoryRegionOps stm32l4x5_usart_base_ops= =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .max_access_size =3D 4, - .min_access_size =3D 4, + .min_access_size =3D 2, .unaligned =3D false }, .impl =3D { .max_access_size =3D 4, - .min_access_size =3D 4, + .min_access_size =3D 2, .unaligned =3D false }, }; diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usa= rt-test.c index c175ff3064..018a8a62bf 100644 --- a/tests/qtest/stm32l4x5_usart-test.c +++ b/tests/qtest/stm32l4x5_usart-test.c @@ -36,6 +36,8 @@ REG32(GTPR, 0x10) REG32(RTOR, 0x14) REG32(RQR, 0x18) REG32(ISR, 0x1C) + FIELD(ISR, REACK, 22, 1) + FIELD(ISR, TEACK, 21, 1) FIELD(ISR, TXE, 7, 1) FIELD(ISR, RXNE, 5, 1) FIELD(ISR, ORE, 3, 1) @@ -191,7 +193,7 @@ static void init_uart(QTestState *qts) =20 /* Enable the transmitter, the receiver and the USART. */ qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), - R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK); + cr1 | R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK); } =20 static void test_write_read(void) @@ -203,6 +205,11 @@ static void test_write_read(void) const uint32_t tdr =3D qtest_readl(qts, USART1_BASE_ADDR + A_TDR); g_assert_cmpuint(tdr, =3D=3D, 0x000001FF); =20 + /* Official STM HAL uses uint16_t for TDR */ + qtest_writew(qts, USART1_BASE_ADDR + A_TDR, 0xFFFF); + const uint16_t tdr16 =3D qtest_readw(qts, USART1_BASE_ADDR + A_TDR); + g_assert_cmpuint(tdr16, =3D=3D, 0x000001FF); + qtest_quit(qts); } =20 @@ -298,6 +305,37 @@ static void test_send_str(void) qtest_quit(qts); } =20 +static void test_ack(void) +{ + uint32_t cr1; + uint32_t isr; + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + + init_uart(qts); + + cr1 =3D qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); + + /* Disable the transmitter and receiver. */ + qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), + cr1 & ~(R_CR1_RE_MASK | R_CR1_TE_MASK)); + + /* Test ISR ACK for transmitter and receiver disabled */ + isr =3D qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); + g_assert_false(isr & R_ISR_TEACK_MASK); + g_assert_false(isr & R_ISR_REACK_MASK); + + /* Enable the transmitter and receiver. */ + qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), + cr1 | (R_CR1_RE_MASK | R_CR1_TE_MASK)); + + /* Test ISR ACK for transmitter and receiver disabled */ + isr =3D qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); + g_assert_true(isr & R_ISR_TEACK_MASK); + g_assert_true(isr & R_ISR_REACK_MASK); + + qtest_quit(qts); +} + int main(int argc, char **argv) { int ret; @@ -310,6 +348,7 @@ int main(int argc, char **argv) qtest_add_func("stm32l4x5/usart/send_char", test_send_char); qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str); qtest_add_func("stm32l4x5/usart/send_str", test_send_str); + qtest_add_func("stm32l4x5/usart/ack", test_ack); ret =3D g_test_run(); =20 return ret; --=20 2.43.0