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[115.64.160.35]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20710f1d4c6sm1703745ad.187.2024.09.06.20.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 20:19:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725679191; x=1726283991; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=VyFIHfk8uZ+7XyQ6F3in7K7dbr0ICc4j2aTIjkZzykzGUQZL+iaKFOE8p2ZBr77R93 L1LPOpcCwczbJ561BPIu8cc5IGQ7mscAAkE8iwMXddjuHbQD73owCvd5Sn2mY0lYxCsJ xIfOQREOk19eTFl49yeEWQaTPv/qZ3uObFqBh5QRKebxnrCN8IgfNdfpDiCW/UbCjoty R2rMeyXj6Zcai4bZtlXLty1cPCbY1dJlCxcXNFdJ6tWw6qOdc6R7DltA+2I57SlnnRm4 6xwSD8FWI/As9FYKis4yFeLd3L/1JkvfevVOkq65CcMLUtypGCA9CMZVax82YCGsW5eO A+UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725679191; x=1726283991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=OZqy4oUVvT5uFww6uyK5Qqar46/HKSTbKNSgFstt87T+cQ8OVFHjct6YwmH/M1+R82 HbVq+i56VJ1NgfHWUMjUZx3NUftDEOV9Djq5RoLWMPc9e3UCK7kDKKxQYEhpdws/jVWX GW+xxJAIy2lGlLTuPyBZr/ePuJ3MSuQHjMhwEMoqdGrq1TSY5ImK7vMmub9ZEQkzEWvc uKSxr+mHFjWv7bAAo5gAUaRJ9RkBco2WdGzv+44bI59G3385+L0zvv1LHlrNbf8CC2El gevvMkmXssCW3yp8RFeM1vv2THsGGVEpXwwG7kvT8jNUZq8+uuQI1NqH1Lmx24c0X80l pdBA== X-Gm-Message-State: AOJu0YxuHV9bGTr77dQHQ7lkQkBaIgi+xMgFuH/zZEhAeNIj9DeZz0vH rpDghYd97QG5vrNs6IP40+vfYeoxgRK1GZWWEwppfp+zg/XyLsK3afL5suqY X-Google-Smtp-Source: AGHT+IGLKO+vkOqS3nX4jPxAsKf/07UdTLheLbJRCq+xlG8Ljp1w9E7SpSRJAf9thF5p9oRzrzKNQQ== X-Received: by 2002:a17:902:fc50:b0:205:4273:7d3e with SMTP id d9443c01a7336-206f064c443mr61078525ad.57.1725679190603; Fri, 06 Sep 2024 20:19:50 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Mark Corbin , Ajeet Singh , Kyle Evans , Richard Henderson Subject: [PATCH v5 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Date: Sat, 7 Sep 2024 13:19:15 +1000 Message-Id: <20240907031927.1908-6-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240907031927.1908-1-itachis@FreeBSD.org> References: <20240907031927.1908-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1725679264216116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_= elf.h new file mode 100644 index 0000000000..4eb915e61e --- /dev/null +++ b/bsd-user/riscv/target_arch_elf.h @@ -0,0 +1,42 @@ +/* + * RISC-V ELF definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#define elf_check_arch(x) ((x) =3D=3D EM_RISCV) +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 +#define ELF_CLASS ELFCLASS64 + +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_RISCV + +#define ELF_HWCAP get_elf_hwcap() +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu =3D RISCV_CPU(thread_cpu); + + return cpu->env.misa_ext_mask; +} + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* TARGET_ARCH_ELF_H */ --=20 2.34.1