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[115.64.160.35]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20710f1d4c6sm1703745ad.187.2024.09.06.20.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 20:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725679180; x=1726283980; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WFvdTr8ItVOjTzK94rYNt0BNQVSxcF+DNvHDFPsSwO0=; b=F/ngugUIyh4Qwfx0KCTh7w9+UyapXmlmGml2QB7gYJYSdcG5Sqb3kvmirKscLxypLK RMVZiOZsVu8oXCE97MvbkJRthpGZVhIga26MLkw8kHlJT9V9ZX870Aa6IWzIvfjRqlIn Uvhm2wOflFT4RduiBlwPjBUplkzTFod3gB9e2Y8BcTU40pxlnPBpTzzKHdx9A2FpXft9 QQogNt47YpxeqRf2wfOxt9W1pvg2tCblLONSsjxnSoHVmxvZUvN54zRvXw/suQZJ6nvL 4IIuoWW/FIp+c8sd1HG3+aoEF5Gl21hU8Wviw6P+YBsCJPbcgijLCVQ1wA6iuAUBTSix jWtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725679180; x=1726283980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WFvdTr8ItVOjTzK94rYNt0BNQVSxcF+DNvHDFPsSwO0=; b=J0dvg3VzueW7BqmoTNeelIKrlcx3UY/Rf3WmXwMlxcy3zsmblrMzrVT29N+6ZkJ0A7 NNtcI43s5sq7hcVmLKhHWube50fLBweY8UY0jxyAmkCP7nhVCZ0Q52/hZnvZeG0ipTSZ V6EM36M3hf8LbB6Qc6o8R1wF3TuRgpa0pYJ1ClxO+ySCYFBZuhOAzaeKuf6xaUj5Eiol 1ZL8OXi6uaSN2wJayLkMeNQMhvdjeBRF26q//BE/jYD40bMsrp5M0h1k2QWR+0j+7oWJ iYo7xyr/3LkNptvP7J35/wxSZcLjXcZERdgHE2LtxjcwB0GjP9o0kVK4zqP39VXDLIX7 fNaQ== X-Gm-Message-State: AOJu0YyyJftK18X/+9sXltXoasiy9W7sMwjBfcLqG0VtCCY4PcjZZeCf 5CVmLX7JBYJICR9jS8KgXthe3X/1yPEwH3/AYC5+fjxBWlgBscfoK/gGQw== X-Google-Smtp-Source: AGHT+IEyVziJZhjBmfDUXH5hcLiDJsDOU+q7+X89ET6HM/SxLsfdSDXpKxv5qWYH9MBB/2TwpnyPDg== X-Received: by 2002:a17:902:bd41:b0:206:b960:2e97 with SMTP id d9443c01a7336-206f0612ed5mr55560995ad.45.1725679179770; Fri, 06 Sep 2024 20:19:39 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Mark Corbin , Ajeet Singh , Jessica Clarke , Richard Henderson Subject: [PATCH v5 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Date: Sat, 7 Sep 2024 13:19:11 +1000 Message-Id: <20240907031927.1908-2-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240907031927.1908-1-itachis@FreeBSD.org> References: <20240907031927.1908-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1725679230812116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 bsd-user/riscv/target_arch_cpu.h diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h new file mode 100644 index 0000000000..e17c910ae9 --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.h @@ -0,0 +1,39 @@ +/* + * RISC-V CPU init and loop + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" + +#define TARGET_DEFAULT_CPU_MODEL "max" + +static inline void target_cpu_init(CPURISCVState *env, + struct target_pt_regs *regs) +{ + int i; + + for (i =3D 1; i < 32; i++) { + env->gpr[i] =3D regs->regs[i]; + } + + env->pc =3D regs->sepc; +} + +#endif /* TARGET_ARCH_CPU_H */ --=20 2.34.1