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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42bb6e355dfsm232251365e9.46.2024.09.05.06.01.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 06:01:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1725541264; x=1726146064; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=o6faGe6s53I53gCyvQfJrfuPm0tizhkfFDlXo8UUwQY=; b=u4MxKlgYM8vWWEqX9vQQRDkMIS0plTaa1GQCQrWvwyl98QWlZFVOvCIP2vhYYCffRt DmJTtueblZr9mSbA4//qhY5B2nwLC3Y0s4nD+HmOZp49jqhKn8RxEnhdqY4gLhgq8esE CrZWi45/dAc1Jtv1+PgIumIJNo/cBvLg8G7wL4GsfLUOvwN38H4tHhNSUM6pZqT049Dz LbNnwlnlzg31EVKp993TQ7iI8CpqoA37Tq2JBeQL/MhlFwc9KH1GeOId32ldJBH83X7v Sf672SYVpV1LIlv0QQXme89hJmH3XHIjJRcXT6onrnA3IMEUGcSEYwk3obIwWM1FwhxI WORg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725541264; x=1726146064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o6faGe6s53I53gCyvQfJrfuPm0tizhkfFDlXo8UUwQY=; b=faBq8IwdsPOwZRdOjCWhVvbbbad1cnG4NILTzfA/qpB3wcGIWNeBoBEAORYJ56Rci5 ei/Uyp0JQ4mkbkYnoi+IBd927gxgXxji6gmJMSPgtrxZriuAhPIpx0vHP5+iwK/V0ovM fCoSVArv16so2HdcCjWK+ugfAg/TrJppRy/IlFWF/rPlGPqAd9orvAzZ/TnVQfCOPFMJ OLO7MYvrlfTdq9Ih7DvmwiEgcPWLpcMXRnPd+RHBJgweyBqk5jRPXyK4ABae3Z1nD9Zl syjcwUGRYD74BRlNnVxNLivwa4HCMZnpt2gDF/E6rU69uXASMKJMfxbdzeh7AjOGR9Tj f3kA== X-Gm-Message-State: AOJu0YxcGUP5RYDluDz83TN6JoRDkDJBMBS8jc5hZo8j0efw8Ie+iIaH xgq/ErS2h0B+N4xBdOF1bGxN4fSnihnsKFQPuMHfwflViyz7MxY8rM6Xn2JEl5tKgmmvREQr1Uq + X-Google-Smtp-Source: AGHT+IFKHrbmeDOu6dc3CyftqWRnX3pyvdOWCWvmPaU766CoCYsIE6qH/k7DtbOLULbw0f8nrtxW0w== X-Received: by 2002:a5d:58e6:0:b0:374:c6b8:50c3 with SMTP id ffacd0b85a97d-3776f92941fmr4434862f8f.32.1725541263906; Thu, 05 Sep 2024 06:01:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/25] target/arm: Allow setting the FPCR.EBF bit for FEAT_EBF16 Date: Thu, 5 Sep 2024 14:00:36 +0100 Message-Id: <20240905130100.298768-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905130100.298768-1-peter.maydell@linaro.org> References: <20240905130100.298768-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1725541385667116600 Content-Type: text/plain; charset="utf-8" FEAT_EBF16 adds one new bit to the FPCR floating point control register. Allow this bit to be read and written when the ID registers indicate the presence of the feature. Note that because this new bit is not in FPSCR_FPCR_MASK the bit is not visible in the AArch32 FPSCR, and FPSCR writes do not affect it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 1 + target/arm/vfp_helper.c | 8 ++++++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index c59ca104fe1..cfb82c23cad 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -556,6 +556,11 @@ static inline bool isar_feature_aa64_bf16(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) !=3D 0; } =20 +static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1; +} + static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a3fd595621..f065756c5c7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1707,6 +1707,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ +#define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index b3698da8ca7..203d37303bd 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -254,6 +254,10 @@ static void vfp_set_fpcr_masked(CPUARMState *env, uint= 32_t val, uint32_t mask) val &=3D ~FPCR_FZ16; } =20 + if (!cpu_isar_feature(aa64_ebf16, cpu)) { + val &=3D ~FPCR_EBF; + } + vfp_set_fpcr_to_host(env, val, mask); =20 if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) { @@ -278,12 +282,12 @@ static void vfp_set_fpcr_masked(CPUARMState *env, uin= t32_t val, uint32_t mask) * We don't implement trapped exception handling, so the * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) * - * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode + * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode, EBF * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI * bits. */ - val &=3D FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16; + val &=3D FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16 | = FPCR_EBF; env->vfp.fpcr &=3D ~mask; env->vfp.fpcr |=3D val; } --=20 2.34.1