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Wed, 04 Sep 2024 22:32:10 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1725460331; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=D40GaT1EAh5YF4VXXTre7aAcaUMpWWM0JcDER8SJKvI=; b=fvq+e/kDo+lVsUEar3edX4gVPu/qevdhdOkjv6SFDfkV0I18w6BmE1JVBZm62Ptg/un1H+2upLB+Dfw3TuInwsCcB9MfUrA/ClDjyzifZHrf7Uj1wQN2FT1sCABCQWVnnL3ltNyV/20VbXsZ7TUai9eflFzRZFouyCXq+YatbhE= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v3 07/14] tcg/riscv: Add support for basic vector opcodes Date: Wed, 4 Sep 2024 22:27:32 +0800 Message-Id: <20240904142739.854-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> References: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 46 ++++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 2 +- 3 files changed, 48 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d73a62b0f2..d4504122a2 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -23,3 +23,4 @@ C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) C_O1_I1(v, r) +C_O1_I1(v, v) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ddb0c8190c..c89d1a5dc9 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -310,6 +310,13 @@ typedef enum { OPC_VS4R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), OPC_VS8R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), =20 + OPC_VADD_VV =3D 0x57 | V_OPIVV, + OPC_VSUB_VV =3D 0x8000057 | V_OPIVV, + OPC_VAND_VV =3D 0x24000057 | V_OPIVV, + OPC_VOR_VV =3D 0x28000057 | V_OPIVV, + OPC_VXOR_VV =3D 0x2c000057 | V_OPIVV, + OPC_VXOR_VI =3D 0x2c000057 | V_OPIVI, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -2291,6 +2298,30 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_add_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VADD_VV, a0, a1, a2, true); + break; + case INDEX_op_sub_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2, true); + break; + case INDEX_op_and_vec: + riscv_set_vec_config_vl(s, type); + tcg_out_opc_vv(s, OPC_VAND_VV, a0, a1, a2, true); + break; + case INDEX_op_or_vec: + riscv_set_vec_config_vl(s, type); + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a1, a2, true); + break; + case INDEX_op_xor_vec: + riscv_set_vec_config_vl(s, type); + tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); + break; + case INDEX_op_not_vec: + riscv_set_vec_config_vl(s, type); + tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true); + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2310,6 +2341,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_not_vec: + return 1; default: return 0; } @@ -2460,6 +2498,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); + case INDEX_op_not_vec: + return C_O1_I1(v, v); + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return C_O1_I2(v, v, v); default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 12a7a37aaa..acb8dfdf16 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -151,7 +151,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_vec 0 #define TCG_TARGET_HAS_nor_vec 0 #define TCG_TARGET_HAS_eqv_vec 0 -#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 --=20 2.43.0