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Wed, 04 Sep 2024 22:31:38 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1725460299; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=2iKtEc4DtzEu4r6Jphm1f0u3H5CKS2ONLfxHet/WOqs=; b=uhWW1P1z1utSArD9QAlc9clQbsHr61B9EINuDF8hWroxc702HSLZvxpmw6PyfwaeGZtAvpWubnNDoHGe6+7iROjjoQzzkKc/0KRVAjfCUSKKYq+pgOeVV+fc7lPRyUfh1q6THjoRdwB3tG8xgnC0ZBDwKpTHMGTDCeS2fG1oQdM= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v3 06/14] tcg/riscv: Implement vector mov/dup{m/i} Date: Wed, 4 Sep 2024 22:27:31 +0800 Message-Id: <20240904142739.854-7-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> References: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4b1079fc6f..ddb0c8190c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -309,6 +309,12 @@ typedef enum { OPC_VS2R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), OPC_VS4R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), OPC_VS8R_V =3D 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), + + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, + OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, + OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, + + OPC_VMVNR_V =3D 0x9e000057 | V_OPIVI, } RISCVInsn; =20 /* @@ -698,6 +704,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) case TCG_TYPE_I64: tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + { + int nf =3D get_vec_type_bytes(type) / riscv_vlenb; + + if (nf !=3D 0) { + tcg_debug_assert(is_power_of_2(nf) && nf <=3D 8); + tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1, true); + } else { + riscv_set_vec_config_vl(s, type); + tcg_out_opc_vv(s, OPC_VMV_V_V, ret, TCG_REG_V0, arg, true); + } + } + break; default: g_assert_not_reached(); } @@ -1106,6 +1127,33 @@ static void tcg_out_addsub2(TCGContext *s, } } =20 +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VMV_V_X, dst, TCG_REG_V0, src, true); + return true; +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offs= et) +{ + tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); + return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t arg) +{ + if (arg < 16 && arg >=3D -16) { + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vi(s, OPC_VMV_V_I, dst, TCG_REG_V0, arg, true); + return; + } + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); + tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); +} + static const struct { RISCVInsn op; bool swap; @@ -2234,6 +2282,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, a2 =3D args[2]; =20 switch (opc) { + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_ld_vec: tcg_out_ld(s, type, a0, a1, a2); break; @@ -2405,6 +2456,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_st_vec: return C_O0_I2(v, r); + case INDEX_op_dup_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); default: --=20 2.43.0