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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 507f659fd6..2dc6befe09 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -315,6 +315,13 @@ typedef enum { OPC_VMSGT_VI =3D 0x7c000057 | V_OPIVI, OPC_VMSGT_VX =3D 0x7c000057 | V_OPIVX, =20 + OPC_VSLL_VV =3D 0x94000057 | V_OPIVV, + OPC_VSLL_VX =3D 0x94000057 | V_OPIVX, + OPC_VSRL_VV =3D 0xa0000057 | V_OPIVV, + OPC_VSRL_VX =3D 0xa0000057 | V_OPIVX, + OPC_VSRA_VV =3D 0xa4000057 | V_OPIVV, + OPC_VSRA_VX =3D 0xa4000057 | V_OPIVX, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -2463,6 +2470,30 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); break; + case INDEX_op_shls_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2, true); + break; + case INDEX_op_shrs_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2, true); + break; + case INDEX_op_sars_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2, true); + break; + case INDEX_op_shlv_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2, true); + break; + case INDEX_op_shrv_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2, true); + break; + case INDEX_op_sarv_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2, true); + break; case INDEX_op_cmpsel_vec: TCGArg a3, a4; int c3, c4; @@ -2560,6 +2591,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: case INDEX_op_cmpsel_vec: return 1; case INDEX_op_cmp_vec: @@ -2731,7 +2768,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); case INDEX_op_cmp_vec: return C_O1_I2(v, v, vL); case INDEX_op_cmpsel_vec: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 7005099810..3bd8b811ef 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -158,8 +158,8 @@ typedef enum { #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 --=20 2.43.0