From nobody Sun Nov 24 11:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1724998758; cv=none; d=zohomail.com; s=zohoarc; b=XdcWDpi3B5Wv3xngBBbhldnpUPJVYYeK6Lfizas7UYH6zoZ3TX7rGhX7J9OAgtt87M8CrPw1qOOYXOVfOeAk/is84SiT05H/mWqZFgYQAruZR7Fw7P3aexqDrOMw79iEksbNl+n5YNLA0DC131trRW0+WzGeMw61BXB5zPEka5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724998758; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J48Krttc2o2DLwm9QXcAjAZXK7O6R59YUwptlmgtAbo=; b=e5RI98IRNkMBY4N4+/1DfX420ZuYFAg22SUF1R2t7azM4XBElCYckk0FoszNg52SEAZ70HYRcjbJHkkr7HqKxVpxO/5Q9V8PIj9L9GluRTr9uMJlFQUiwR3xpw7jU61gIyBVBwQHIstRgOsV552DbEJjomNImfq6OLU7dYDSdHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724998758177952.5059355167534; Thu, 29 Aug 2024 23:19:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjuyR-00072S-IQ; Fri, 30 Aug 2024 02:19:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjuyP-0006vD-Oi; Fri, 30 Aug 2024 02:19:05 -0400 Received: from out30-130.freemail.mail.aliyun.com ([115.124.30.130]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjuyN-0004sz-6G; Fri, 30 Aug 2024 02:19:05 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WDvaTjR_1724998733) by smtp.aliyun-inc.com; Fri, 30 Aug 2024 14:18:54 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1724998737; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=J48Krttc2o2DLwm9QXcAjAZXK7O6R59YUwptlmgtAbo=; b=F2SmCjgysYvRu3kYC2fwSAwG3MMmVJfge33vWGHb6F2AN/6a7BvBS3vAOaw6RRfh0LmxPWWdXtO+yH9dEWttEqQR8gKXH0XVn+TQISm9WiiG3fzAwWO5fjTOThvrCLdxRELVyVdqjhD2Cvn8T0qjYNcyiRO6dpeylHsaChcz/Sc= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support Date: Fri, 30 Aug 2024 14:15:57 +0800 Message-Id: <20240830061607.1940-5-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.130; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-130.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1724998758404116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multiplier) Other vector operation parameters This configuration is crucial for defining subsequent vector operation behavior. To optimize performance, the configuration process is managed dynamically: 1. Reconfiguration using vset{i}vl{i} is necessary when SEW or vector register group width changes. 2. The vset instruction can be omitted when configuration remains unchanged. This optimization is only effective within a single TB. Each TB requires reconfiguration at its start, as the current state cannot be obtained from hardware. Signed-off-by: TANG Tiancheng Signed-off-by: Weiwei Li Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 104 +++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 5ef1538aed..49d01b8775 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -119,6 +119,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKin= d kind, int slot) #define GET_VREG_SET(vlen) (vlen =3D=3D 64 ? ALL_QVECTOR_REG_GROUPS : \ (vlen =3D=3D 128 ? ALL_DVECTOR_REG_GROUPS : \ ALL_VECTOR_REGS)) +#define riscv_vlenb (riscv_vlen / 8) =20 #define sextreg sextract64 =20 @@ -168,6 +169,18 @@ static bool tcg_target_const_match(int64_t val, int ct, * RISC-V Base ISA opcodes (IM) */ =20 +#define V_OPIVV (0x0 << 12) +#define V_OPFVV (0x1 << 12) +#define V_OPMVV (0x2 << 12) +#define V_OPIVI (0x3 << 12) +#define V_OPIVX (0x4 << 12) +#define V_OPFVF (0x5 << 12) +#define V_OPMVX (0x6 << 12) +#define V_OPCFG (0x7 << 12) + +#define V_SUMOP (0x0 << 20) +#define V_LUMOP (0x0 << 20) + typedef enum { OPC_ADD =3D 0x33, OPC_ADDI =3D 0x13, @@ -263,6 +276,11 @@ typedef enum { /* Zicond: integer conditional operations */ OPC_CZERO_EQZ =3D 0x0e005033, OPC_CZERO_NEZ =3D 0x0e007033, + + /* V: Vector extension 1.0 */ + OPC_VSETVLI =3D 0x57 | V_OPCFG, + OPC_VSETIVLI =3D 0xc0000057 | V_OPCFG, + OPC_VSETVL =3D 0x80000057 | V_OPCFG, } RISCVInsn; =20 /* @@ -355,6 +373,35 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uin= t32_t imm) return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); } =20 +typedef enum { + VTA_TU =3D 0, + VTA_TA, +} RISCVVta; + +typedef enum { + VMA_MU =3D 0, + VMA_MA, +} RISCVVma; + +typedef enum { + VLMUL_M1 =3D 0, /* LMUL=3D1 */ + VLMUL_M2, /* LMUL=3D2 */ + VLMUL_M4, /* LMUL=3D4 */ + VLMUL_M8, /* LMUL=3D8 */ + VLMUL_RESERVED, + VLMUL_MF8, /* LMUL=3D1/8 */ + VLMUL_MF4, /* LMUL=3D1/4 */ + VLMUL_MF2, /* LMUL=3D1/2 */ +} RISCVVlmul; +#define LMUL_MAX 8 + +static int32_t encode_vtypei(RISCVVta vta, RISCVVma vma, + unsigned vsew, RISCVVlmul vlmul) +{ + return (vma & 0x1) << 7 | (vta & 0x1) << 6 | (vsew & 0x7) << 3 | + (vlmul & 0x7); +} + /* * RISC-V instruction emitters */ @@ -484,6 +531,12 @@ static void tcg_out_opc_reg_vec_i(TCGContext *s, RISCV= Insn opc, tcg_out32(s, encode_r(opc, rd, (imm & 0x1f), vs2) | (vm << 25)); } =20 +static void tcg_out_opc_vec_config(TCGContext *s, RISCVInsn opc, + TCGReg rd, uint32_t avl, int32_t vtypei) +{ + tcg_out32(s, encode_i(opc, rd, avl, vtypei)); +} + /* vm=3D0 (vm =3D false) means vector masking ENABLED. */ #define tcg_out_opc_vv(s, opc, vd, vs2, vs1, vm) \ tcg_out_opc_reg_vec(s, opc, vd, vs1, vs2, vm); @@ -498,12 +551,62 @@ static void tcg_out_opc_reg_vec_i(TCGContext *s, RISC= VInsn opc, #define tcg_out_opc_vi(s, opc, vd, vs2, imm, vm) \ tcg_out_opc_reg_vec_i(s, opc, vd, imm, vs2, vm); =20 +#define tcg_out_opc_vconfig(s, opc, rd, avl, vtypei) \ + tcg_out_opc_vec_config(s, opc, rd, avl, vtypei); + /* * Only unit-stride addressing implemented; may extend in future. */ #define tcg_out_opc_ldst_vec(s, opc, vs3_vd, rs1, vm) \ tcg_out_opc_reg_vec(s, opc, vs3_vd, rs1, 0, vm); =20 +static void tcg_out_vsetvl(TCGContext *s, uint32_t avl, int vtypei) +{ + if (avl < 32) { + tcg_out_opc_vconfig(s, OPC_VSETIVLI, TCG_REG_ZERO, avl, vtypei); + } else { + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, avl); + tcg_out_opc_vconfig(s, OPC_VSETVLI, TCG_REG_ZERO, TCG_REG_TMP0, vt= ypei); + } +} + +/* + * TODO: If the vtype value is not supported by the implementation, + * then the vill bit is set in vtype, the remaining bits in + * vtype are set to zero, and the vl register is also set to zero + */ + +static __thread int prev_vtypei; + +#define get_vlmax(vsew) (riscv_vlen / (8 << vsew) * (LMUL_MAX)) +#define get_vec_type_bytes(type) (type >=3D TCG_TYPE_V64 ? \ + (8 << (type - TCG_TYPE_V64)) : 0) +#define calc_vlmul(oprsz) (ctzl(oprsz / riscv_vlenb)) + +static void tcg_target_set_vec_config(TCGContext *s, TCGType type, + unsigned vece) +{ + unsigned vsew, oprsz, avl; + int vtypei; + RISCVVlmul vlmul; + + vsew =3D vece; + oprsz =3D get_vec_type_bytes(type); + avl =3D oprsz / (1 << vece); + vlmul =3D oprsz > riscv_vlenb ? + calc_vlmul(oprsz) : VLMUL_M1; + vtypei =3D encode_vtypei(VTA_TA, VMA_MA, vsew, vlmul); + + tcg_debug_assert(avl <=3D get_vlmax(vsew)); + tcg_debug_assert(vlmul <=3D VLMUL_RESERVED); + tcg_debug_assert(vsew <=3D MO_64); + + if (vtypei !=3D prev_vtypei) { + prev_vtypei =3D vtypei; + tcg_out_vsetvl(s, avl, vtypei); + } +} + /* * TCG intrinsics */ @@ -2152,6 +2255,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 static void tcg_out_tb_start(TCGContext *s) { + prev_vtypei =3D -1; /* nothing to do */ } =20 --=20 2.43.0