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Fri, 30 Aug 2024 14:23:35 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1724999015; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=340xhIGayUIyfd9HFZ6XOEwO2amdYAEcmRyAm2RnTPs=; b=m7qEIcVhRFNE3n2VVofVmWhvlO9Ld7/7kWpBsncOXVWC3J2Br6Y4IJDO73urVhhr//0VyiGuGGPg4CKO+D5g/+yyIpqPmhr+R/fH1ZdTsyecePm5QfJro++5z0TTW3H0W9IL6Om+37S2C3EEVS0PetTi9i/vnSLM4DtarFU6OQ4= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops Date: Fri, 30 Aug 2024 14:16:06 +0800 Message-Id: <20240830061607.1940-14-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 98 +++++++++++++++++++++++++++++++++++++- tcg/riscv/tcg-target.h | 8 ++-- tcg/riscv/tcg-target.opc.h | 3 ++ 3 files changed, 104 insertions(+), 5 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 31e161c5bc..6560d3381a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -358,10 +358,13 @@ typedef enum { OPC_VMSGT_VX =3D 0x7c000057 | V_OPIVX, =20 OPC_VSLL_VV =3D 0x94000057 | V_OPIVV, + OPC_VSLL_VI =3D 0x94000057 | V_OPIVI, OPC_VSLL_VX =3D 0x94000057 | V_OPIVX, OPC_VSRL_VV =3D 0xa0000057 | V_OPIVV, + OPC_VSRL_VI =3D 0xa0000057 | V_OPIVI, OPC_VSRL_VX =3D 0xa0000057 | V_OPIVX, OPC_VSRA_VV =3D 0xa4000057 | V_OPIVV, + OPC_VSRA_VI =3D 0xa4000057 | V_OPIVI, OPC_VSRA_VX =3D 0xa4000057 | V_OPIVX, =20 OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, @@ -2477,6 +2480,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2, true); break; + case INDEX_op_rvv_shli_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vi(s, OPC_VSLL_VI, a0, a1, a2, true); + break; + case INDEX_op_rvv_shri_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vi(s, OPC_VSRL_VI, a0, a1, a2, true); + break; + case INDEX_op_rvv_sari_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vi(s, OPC_VSRA_VI, a0, a1, a2, true); + break; case INDEX_op_rvv_cmp_vx: riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_cmp_vec_vx(s, a2, a0, a1); @@ -2561,7 +2576,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1; + TCGv_vec v0, v1, v2, t1; + TCGv_i32 t2; TCGArg a2, a3; =20 va_start(va, a0); @@ -2589,6 +2605,69 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, } } break; + case INDEX_op_shli_vec: + if (a2 > 31) { + tcg_gen_shls_vec(vece, v0, v1, tcg_constant_i32(a2)); + } else { + vec_gen_3(INDEX_op_rvv_shli_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), a2); + } + break; + case INDEX_op_shri_vec: + if (a2 > 31) { + tcg_gen_shrs_vec(vece, v0, v1, tcg_constant_i32(a2)); + } else { + vec_gen_3(INDEX_op_rvv_shri_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), a2); + } + break; + case INDEX_op_sari_vec: + if (a2 > 31) { + tcg_gen_sars_vec(vece, v0, v1, tcg_constant_i32(a2)); + } else { + vec_gen_3(INDEX_op_rvv_sari_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), a2); + } + break; + case INDEX_op_rotli_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_shli_vec(vece, t1, v1, a2); + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - a2); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + case INDEX_op_rotls_vec: + t1 =3D tcg_temp_new_vec(type); + t2 =3D tcg_temp_new_i32(); + tcg_gen_neg_i32(t2, temp_tcgv_i32(arg_temp(a2))); + tcg_gen_shrs_vec(vece, v0, v1, t2); + tcg_gen_shls_vec(vece, t1, v1, temp_tcgv_i32(arg_temp(a2))); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + tcg_temp_free_i32(t2); + break; + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + case INDEX_op_rotrv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; default: g_assert_not_reached(); } @@ -2622,6 +2701,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sarv_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_shri_vec: + case INDEX_op_shli_vec: + case INDEX_op_sari_vec: + case INDEX_op_rotls_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_rotli_vec: return -1; default: return 0; @@ -2775,6 +2861,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) return C_O1_I1(v, r); case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_rotli_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + case INDEX_op_rvv_shli_vec: + case INDEX_op_rvv_shri_vec: + case INDEX_op_rvv_sari_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2793,10 +2886,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return C_O1_I2(v, v, v); case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: return C_O1_I2(v, v, r); case INDEX_op_rvv_merge_vec: return C_O1_I2(v, v, vK); diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 41c6c446e8..eb5129a976 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -154,10 +154,10 @@ typedef enum { #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 0 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_roti_vec -1 +#define TCG_TARGET_HAS_rots_vec -1 +#define TCG_TARGET_HAS_rotv_vec -1 +#define TCG_TARGET_HAS_shi_vec -1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 diff --git a/tcg/riscv/tcg-target.opc.h b/tcg/riscv/tcg-target.opc.h index 8eb0daf0a7..9f31286025 100644 --- a/tcg/riscv/tcg-target.opc.h +++ b/tcg/riscv/tcg-target.opc.h @@ -15,3 +15,6 @@ DEF(rvv_cmp_vi, 0, 1, 2, IMPLVEC) DEF(rvv_cmp_vx, 0, 2, 1, IMPLVEC) DEF(rvv_cmp_vv, 0, 2, 1, IMPLVEC) DEF(rvv_merge_vec, 1, 2, 0, IMPLVEC) +DEF(rvv_shli_vec, 1, 1, 1, IMPLVEC) +DEF(rvv_shri_vec, 1, 1, 1, IMPLVEC) +DEF(rvv_sari_vec, 1, 1, 1, IMPLVEC) --=20 2.43.0