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Fri, 30 Aug 2024 14:23:04 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1724998984; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=VHqgC1hp5BN3oPbdIlhA36FZQo9lW36ePkBfcKAoRwY=; b=MGxugcEuxZwiSMYNKAqmaatfTDCNtU/Pvpl+yjQMfZtGEXoU1vBfHIhWmwOXlTUPGThpJXsGrw5pQ0gyoGozpVd6MEVsm15I5gl+gmJ/5Q4klNuEqtEDNXnlFus7kml8FK+o5LVXDMDVJHmjBWZgIEPTw/WTlaWnjfHRtb7qqIM= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops Date: Fri, 30 Aug 2024 14:16:05 +0800 Message-Id: <20240830061607.1940-13-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 6c9ad5188b..3154fe8ea8 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -29,3 +29,4 @@ C_O1_I1(v, v) C_O1_I2(v, v, v) C_O1_I2(v, v, vi) C_O1_I2(v, v, vK) +C_O1_I2(v, v, r) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 7de2da3571..31e161c5bc 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -357,6 +357,13 @@ typedef enum { OPC_VMSGT_VI =3D 0x7c000057 | V_OPIVI, OPC_VMSGT_VX =3D 0x7c000057 | V_OPIVX, =20 + OPC_VSLL_VV =3D 0x94000057 | V_OPIVV, + OPC_VSLL_VX =3D 0x94000057 | V_OPIVX, + OPC_VSRL_VV =3D 0xa0000057 | V_OPIVV, + OPC_VSRL_VX =3D 0xa0000057 | V_OPIVX, + OPC_VSRA_VV =3D 0xa4000057 | V_OPIVV, + OPC_VSRA_VX =3D 0xa4000057 | V_OPIVX, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -2446,6 +2453,30 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); break; + case INDEX_op_shls_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2, true); + break; + case INDEX_op_shrs_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2, true); + break; + case INDEX_op_sars_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2, true); + break; + case INDEX_op_shlv_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2, true); + break; + case INDEX_op_shrv_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2, true); + break; + case INDEX_op_sarv_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmp_vx: riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_cmp_vec_vx(s, a2, a0, a1); @@ -2583,6 +2614,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2753,7 +2790,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); case INDEX_op_rvv_merge_vec: return C_O1_I2(v, v, vK); case INDEX_op_rvv_cmp_vi: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 35e7086ad7..41c6c446e8 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -158,8 +158,8 @@ typedef enum { #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 --=20 2.43.0