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Fri, 30 Aug 2024 14:22:33 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1724998953; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/zsFQC12bhfJKf5nzHbKeJO0WCXHnFNVHyGdYjhRr1c=; b=BD8iHMJKBUD1Q0gqyrCFvCqdSqnrqZUZTgdli26dQb+z3iYMwfH6z916XM6EmjHUE8sWKVtEL8wtxXy+3hN9aaf9fOw6oK3WyaxDqcdYwqcBKsU0/Gk/lpwNGYahApjwFOobstEaRnpnIr5zcfNgo+ipiY/5EeIaatEa4aWW1bI= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops Date: Fri, 30 Aug 2024 14:16:04 +0800 Message-Id: <20240830061607.1940-12-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 01d03a9208..7de2da3571 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -329,6 +329,11 @@ typedef enum { OPC_VSADDU_VV =3D 0x80000057 | V_OPIVV, OPC_VSSUBU_VV =3D 0x88000057 | V_OPIVV, =20 + OPC_VMAX_VV =3D 0x1c000057 | V_OPIVV, + OPC_VMAXU_VV =3D 0x18000057 | V_OPIVV, + OPC_VMIN_VV =3D 0x14000057 | V_OPIVV, + OPC_VMINU_VV =3D 0x10000057 | V_OPIVV, + OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, @@ -2425,6 +2430,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); break; + case INDEX_op_smax_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VMAX_VV, a0, a1, a2, true); + break; + case INDEX_op_smin_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VMIN_VV, a0, a1, a2, true); + break; + case INDEX_op_umax_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VMAXU_VV, a0, a1, a2, true); + break; + case INDEX_op_umin_vec: + riscv_set_vec_config_vl_vece(s, type, vece); + tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmp_vx: riscv_set_vec_config_vl_vece(s, type, vece); tcg_out_cmp_vec_vx(s, a2, a0, a1); @@ -2558,6 +2579,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2724,6 +2749,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_rvv_merge_vec: return C_O1_I2(v, v, vK); diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 21251f8b23..35e7086ad7 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -162,7 +162,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 --=20 2.43.0