From nobody Sun Nov 24 09:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1724974680; cv=none; d=zohomail.com; s=zohoarc; b=Sh4Ia2qBMJxiQVMaDXARt4w650AQb5sCGIagSo6CrEGlsRVwbYoctv3fURWf5TtaeE3/PR+p9vka5bUNyQMEGAVbLQU4m0iR4Qqrk84TM2/WZoaBhS7svdX5FUoBTOPLcSHPqmgGmdaUBZBop4I9Ot3rIJsA7Cp2+MtUeTH7nBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724974680; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ikLykblqc83vbTXDLpC9Aaa03TXnumYmpD+XseiMR/s=; b=MyogJj8yeM4OgA2sEkhQe2gFcHj21NsrXGruLDVZWLqyKrNgcKLPLaIfQ5NITQpk+hl5G2TXLglohYicslCZ6GYYp1pCpW1a0GraSF4lAtE+Ba2UE9k+mFv6hOMoQiRxSwdktdnC86UGAQU6W4M7HVb3cntwi1p6pdqd1sstzrM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724974680214353.4193632550922; Thu, 29 Aug 2024 16:38:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjofM-0004Cc-BA; Thu, 29 Aug 2024 19:35:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjofI-0003ye-Ff for qemu-devel@nongnu.org; Thu, 29 Aug 2024 19:34:56 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sjofC-0003BU-I5 for qemu-devel@nongnu.org; Thu, 29 Aug 2024 19:34:56 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2d3d662631aso925441a91.1 for ; Thu, 29 Aug 2024 16:34:50 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d85b13df55sm2331074a91.27.2024.08.29.16.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2024 16:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724974488; x=1725579288; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ikLykblqc83vbTXDLpC9Aaa03TXnumYmpD+XseiMR/s=; b=d7e8ibQwmN5hIJ9ARUsmJlBjoIAU5Ao3mJp3kRFrXbhbgRrU43PcmREqpw+s1tvCVs TlorK9Od4KLnIKmb9iVExIESGpV/G54uCcmY2fmb4sw+VkSbyxjVehPMHHqP5CiSdQjK +aX8Hc5OEosRy1idkoHpbhdkf6u16WLA+B8/IEw6Ux+voOUeLXygxtEfTa1KPVpQkAaw 001ykFuvK714eFbxvf1aT9BfU7PMIEzXFa/BGo4BnLCwjmfSAHh0uKIIMmgIbHkIWEJU Ym+/SwGl12NXNWa9cFaIec+S4ftx2SI3LAXZZl0vJajtbqQ2IBTAxxdFoJPLADak1sKZ nN5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724974488; x=1725579288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ikLykblqc83vbTXDLpC9Aaa03TXnumYmpD+XseiMR/s=; b=VyqTAhPR/qsdMc9LFeHHtZGWnMKeHOYpWHEqoK3J8JuwOarTGfgXT4RzeTCkOvuUgo xunQHLqAJlIGeEVGoA42F87HC4DacGj7exAFiKtUfs0kOTpDxWGonPSBQPg/8WPyzlnN 3f6u7oO/9Dt3Bwio15WhfYkFMvizfepKApQB7O+KlU8q2cn7AcmAD/oyRBVVPVocdwmu dOEuarpfs9Q6z637VrUnY3L1BJ9S0SFrTd+y9hAuA/10Uq8qt1BDLKJR6EMeCBY8ELJZ lYNyPTsiLzbLTepCr2DcM7XCIR2+AU5ze493fpr1E3rW/iFMMc3s5ahq9DBaHX16+gce ku3g== X-Forwarded-Encrypted: i=1; AJvYcCUOmNccsDTmUNjYK8PvXPSGOUSXNtzLBJvIbfBiyoGUI/gPjSrIMy04oDPO2LDjywLX9spw8kpsSpbY@nongnu.org X-Gm-Message-State: AOJu0Yyl08pJ2kElGpQqDvJkkyJx8kSO1QKcwYoAgzVMziExQNmLSJ1W +9gvlU59dF3BzKch3wGLWuvW8uRQHGUPQFZsAl4b/tW21BrpIfMFC5Qb0wqOW6M= X-Google-Smtp-Source: AGHT+IEKmfJiejKPvbXVp0yPaAGTeG4qgI3HX5Y3sW44s3zlGIhgBqnDTQX92gj0W8BKT3J1slRADw== X-Received: by 2002:a17:90b:4a0b:b0:2d3:ca6d:a10a with SMTP id 98e67ed59e1d1-2d85616ebddmr5462734a91.1.1724974487903; Thu, 29 Aug 2024 16:34:47 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Richard Henderson , Alistair Francis Subject: [PATCH v12 14/20] target/riscv: AMO operations always raise store/AMO fault Date: Thu, 29 Aug 2024 16:34:18 -0700 Message-ID: <20240829233425.1005029-15-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240829233425.1005029-1-debug@rivosinc.com> References: <20240829233425.1005029-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=debug@rivosinc.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1724974681220116600 Content-Type: text/plain; charset="utf-8" This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 9 ++++++++- target/riscv/cpu_helper.c | 20 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 1 + target/riscv/translate.c | 2 +- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e758f4497e..0a13604e37 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -46,8 +46,13 @@ typedef struct CPUArchState CPURISCVState; /* * RISC-V-specific extra insn start words: * 1: Original instruction opcode + * 2: more information about instruction */ -#define TARGET_INSN_START_EXTRA_WORDS 1 +#define TARGET_INSN_START_EXTRA_WORDS 2 +/* + * b0: Whether a instruction always raise a store AMO or not. + */ +#define RISCV_UW2_ALWAYS_STORE_AMO 1 =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 @@ -226,6 +231,8 @@ struct CPUArchState { bool elp; /* shadow stack register for zicfiss extension */ target_ulong ssp; + /* env place holder for extra word 2 during unwind */ + target_ulong excp_uw2; /* sw check code for sw check exception */ target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f0c75d8b0a..3692724cbc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1748,6 +1748,22 @@ static target_ulong riscv_transformed_insn(CPURISCVS= tate *env, return xinsn; } =20 +static target_ulong promote_load_fault(target_ulong orig_cause) +{ + switch (orig_cause) { + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: + return RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; + + case RISCV_EXCP_LOAD_ACCESS_FAULT: + return RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + + case RISCV_EXCP_LOAD_PAGE_FAULT: + return RISCV_EXCP_STORE_PAGE_FAULT; + } + + /* if no promotion, return original cause */ + return orig_cause; +} /* * Handle Traps * @@ -1759,6 +1775,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; bool write_gva =3D false; + bool always_storeamo =3D (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); uint64_t s; =20 /* @@ -1792,6 +1809,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + if (always_storeamo) { + cause =3D promote_load_fault(cause); + } write_gva =3D env->two_stage_lookup; tval =3D env->badaddr; if (env->two_stage_indirect_lookup) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4da26cb926..83771303a8 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -129,6 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->pc =3D pc; } env->bins =3D data[1]; + env->excp_uw2 =3D data[2]; } =20 static const TCGCPUOps riscv_tcg_ops =3D { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index afa2ed4e3a..0322597bf6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1264,7 +1264,7 @@ static void riscv_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) pc_next &=3D ~TARGET_PAGE_MASK; } =20 - tcg_gen_insn_start(pc_next, 0); + tcg_gen_insn_start(pc_next, 0, 0); ctx->insn_start_updated =3D false; } =20 --=20 2.44.0