From nobody Sun Nov 24 10:48:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1724867628; cv=none; d=zohomail.com; s=zohoarc; b=IDe4W1keETzl1LmPoIyZMjdLMUFs6AqE0mmbXlzhjK54XnUm7L43S0nTWdxO4u/Gw8ik4g07Ly8DftmwvB9y8wU2FhOc/PFrVqTCH13WeII4O+vAd1C/jUHb/Sw22JH5Pz4t0z+kSKGrofsSkZUuo+c062n9miE7afIT+LaTnqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724867628; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fvGH26X0+vKupgaNF4mDFcjO25Iuuu3HUu52oa4zQIQ=; b=iSeUvST14AloCWw2tpDGEmH3d231AEdMcAwPkZXqCzFt613C3/5NsfoLqZKQn9+WkNONYtAfkXcG0kAarlQSBd3yqcD90RR8fA2Fg87B9Bz37axdhcijcufmpsfaSkoIZRdDEBiVrQ8R59WH34qWAZnJ19u891BOM1FgFcT3Rso= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724867628730333.90481020000925; Wed, 28 Aug 2024 10:53:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjMm5-00078a-Eu; Wed, 28 Aug 2024 13:48:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjMm2-0006xd-Mi for qemu-devel@nongnu.org; Wed, 28 Aug 2024 13:48:02 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sjMlu-0004RE-Vh for qemu-devel@nongnu.org; Wed, 28 Aug 2024 13:48:02 -0400 Received: by mail-ot1-x329.google.com with SMTP id 46e09a7af769-709339c91f9so5121643a34.0 for ; Wed, 28 Aug 2024 10:47:54 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9acdcf7dsm9778316a12.50.2024.08.28.10.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 10:47:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724867274; x=1725472074; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fvGH26X0+vKupgaNF4mDFcjO25Iuuu3HUu52oa4zQIQ=; b=p9iEXw9ae3THUWi2Vks//mqIxCO0u7Cm1K6vRFOTEgHx+UtXh99bMgnne3Rtz3pt5h EmYeUaE/Z/KsN9BxJtJ2qu3br8jejn9TV0mJK8veg44/GoOVu9guM50h+7fSMJqLJoed WsiJ3vYrhPlOS0RvoEYSDTfhIc/aIenDMWm3TQX1HB5yWHlz71kOhnM06J/DFq10gx+3 0YpG1DoW/+nFrO3mtANYaWP0ROrH25boYjK1bHXGe/AvvsbmNcnwFG6BNSSG84EyaX+V G/VOin9tjbVR0Al3wLBRWdP/CPQ8CEqGmZ4cNRrzl8+koeeQMog2qZrhrcKywV453a+F zWbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724867274; x=1725472074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fvGH26X0+vKupgaNF4mDFcjO25Iuuu3HUu52oa4zQIQ=; b=OarXszKbhQdHloutZwllZyFlZ/KCeVMk23quVcQZB2tOPQx0DbpJInjin6H4MTvqg8 oDDuloYftx0q/cGZ87JKfYEE1WFEBZumX/AWH6Iq6U3kQqjI1PbT6x+vUttNkXRRpOSJ NKR9XIhKpBaiaQa9ThIO0O7SdLCFq43QxHbJFqoj+HrHDMJwT5YB6keSjAHUqbFGNHCp 673NkD7xAtf6gsWbgT/EX+VOFb7q1gpGwtQmEOpiHDx0lai5geW/7HDDMXV3vQRvCwDp w7enYti+I9HLobdfLQb9Xu5fzeISfFVG42/ZKi5AIqIc8WyOq29n8DoJyRoraE8Spgz5 AZbw== X-Forwarded-Encrypted: i=1; AJvYcCXsLDDeg8/fJLjUQ3QG/5PAiTBmLZUXiau3Al+vwIflfALUe4+rCGpd5R98xuI4O90SRhwLOkS8ZSp3@nongnu.org X-Gm-Message-State: AOJu0YwQuzL7wgnz8445y5gRO2d/Mf5bk8iF/ESWdzkpdSOQ4RJATb8U g9mClAkkMjBWsAUyvS+nbNcB6G+4+SjW0LT6Q36z3vjTkxSdipgndJCE4LgXtmSmFxPlCReYEzp z X-Google-Smtp-Source: AGHT+IH7NKQoVjvjZgdNECPUVYcryUDwUyrDqxUsTOZ9+1XJcOeGgLv3MfcpcVtNsRsh4lKKdxtR7A== X-Received: by 2002:a05:6358:93a8:b0:1a6:72b8:d08f with SMTP id e5c5f4694b2df-1b603f7df23mr48944655d.29.1724867273624; Wed, 28 Aug 2024 10:47:53 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Richard Henderson , Alistair Francis Subject: [PATCH v11 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Date: Wed, 28 Aug 2024 10:47:24 -0700 Message-ID: <20240828174739.714313-7-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240828174739.714313-1-debug@rivosinc.com> References: <20240828174739.714313-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=debug@rivosinc.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1724867629591116600 Content-Type: text/plain; charset="utf-8" zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval =3D 2. This patch implements the mechanism using TCG. Target architecture branch instruction must define the end of a TB. Using this property, during translation of branch instruction, TB flag =3D FCFI_LP_EXPECTED can be set. Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a flag (fcfi_lp_expected) can be set in DisasContext. If `lpad` gets translated, fcfi_lp_expected flag in DisasContext can be cleared. Else it'll fault. Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/translate.c | 23 +++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a0f14c759e..f372a4074b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -606,6 +606,9 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, PRIV, 24, 2) FIELD(TB_FLAGS, AXL, 26, 2) +/* zicfilp needs a TB flag to track indirect branches */ +FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1) +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b05ebe6f29..900769ce60 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -685,6 +685,9 @@ typedef enum RISCVException { RISCV_EXCP_SEMIHOST =3D 0x3f, } RISCVException; =20 +/* zicfilp defines lp violation results in sw check with tval =3D 2*/ +#define RISCV_EXCP_SW_CHECK_FCFI_TVAL 2 + #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fffd865cb4..c3820eff8f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -132,6 +132,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } =20 + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + #ifdef CONFIG_USER_ONLY fs =3D EXT_STATUS_DIRTY; vs =3D EXT_STATUS_DIRTY; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index acba90f170..b5c0511b4b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -116,6 +116,9 @@ typedef struct DisasContext { bool frm_valid; bool insn_start_updated; const GPtrArray *decoders; + /* zicfilp extension. fcfi_enabled, lp expected or not */ + bool fcfi_enabled; + bool fcfi_lp_expected; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1238,6 +1241,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); + ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); + ctx->fcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; @@ -1270,6 +1275,24 @@ static void riscv_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) decode_opc(env, ctx, opcode16); ctx->base.pc_next +=3D ctx->cur_insn_len; =20 + /* + * If 'fcfi_lp_expected' is still true after processing the instructio= n, + * then we did not see an 'lpad' instruction, and must raise an except= ion. + * Insert code to raise the exception at the start of the insn; any ot= her + * code the insn may have emitted will be deleted as dead code followi= ng + * the noreturn exception + */ + if (ctx->fcfi_lp_expected) { + /* Emit after insn_start, i.e. before the op following insn_start.= */ + tcg_ctx->emit_before_op =3D QTAILQ_NEXT(ctx->base.insn_start, link= ); + tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); + gen_helper_raise_exception(tcg_env, + tcg_constant_i32(RISCV_EXCP_SW_CHECK)); + tcg_ctx->emit_before_op =3D NULL; + ctx->base.is_jmp =3D DISAS_NORETURN; + } + /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next))= { --=20 2.44.0