From nobody Sun Nov 24 11:02:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1724867612; cv=none; d=zohomail.com; s=zohoarc; b=KFj3PxKfPi8DK5vAY4d8iDkY/dfwLUrS+8EMc3HcPKnuoWB3nakQ2k8pziDwSVEZ19dcrNshzrb8fzHxKex2Ye5YN6f7/CuTV1m7UNNlCA3ArsPICC/4VgMZkVcG9POJKjBE+q0zjzss83nwd6Gy5hmlMt7XQQ5hjzb3bYPFd8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724867612; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nfT0nIMWBIbJcaqmjwnW5/0Iuog81wXS/GOvLXNs2Eg=; b=IKSICtoNjryzLIo7R45ZjvhDnTE4K9UHcYNrqlXP1yNtF94TZe0yWOqnLDqwucKlXJZQ7V6OGMwuMPtLebaewE+Fq3ppe95A499N5FCDUMYbE/w3dxGdXTKcHWINw7nVkow8znUBdzniguvtrTOYiAUj/0BtNgFlJJPmt52Ncjw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724867612288860.6716346599443; Wed, 28 Aug 2024 10:53:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjMmH-0007we-6n; Wed, 28 Aug 2024 13:48:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjMm9-0007OO-IY for qemu-devel@nongnu.org; Wed, 28 Aug 2024 13:48:09 -0400 Received: from mail-ot1-x331.google.com ([2607:f8b0:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sjMm4-0004Tt-4C for qemu-devel@nongnu.org; Wed, 28 Aug 2024 13:48:08 -0400 Received: by mail-ot1-x331.google.com with SMTP id 46e09a7af769-7094641d4e6so3472287a34.3 for ; Wed, 28 Aug 2024 10:48:03 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9acdcf7dsm9778316a12.50.2024.08.28.10.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 10:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724867283; x=1725472083; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nfT0nIMWBIbJcaqmjwnW5/0Iuog81wXS/GOvLXNs2Eg=; b=0ZiabdUX7YWfFIRuuYV6U/X8dP1RSLkLgTEfbM86SZx8Jng9D54waFwVdTzp6un4r9 Bn6XjBBEmL78ppzgCWuqZLlYPmF6N5sgtNaenJyg+/OTL/R3T6TbaASAB2XdVOzqtubf k0Kk03/q3YkXEuz0pampbLX0/xJZrxKyfIh+RbZXgEv+rREBJ7KL3G5WdjgVNVdyaz31 E0/+Q07vz5HgIj7gmwYCovsys4ut9Zki6mpq5m7frid/ifh6tJ7CfmhJ0ZXH2G3C0f3l DAucVn2VXkq3s2mj0tMZQXOYI6Q6vzZxhwehzUb21vJ3Ew5xkTNCKoeyun2REvPwBtwv s1xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724867283; x=1725472083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nfT0nIMWBIbJcaqmjwnW5/0Iuog81wXS/GOvLXNs2Eg=; b=ogA4a5TsMZGIomvW/BW3PSk84w7C97WPr7RPqWMJZC8KWTdegkow2BMTUYW5cPO1Qb Ul00O4/YopG/XRWC4FJR/P1TYQZa40/xi7F92blZA2HYB3M6JhVWFDwszigaOeF++K6X xtdK9J7/URjqAMgINBL/URGTgZ5kWkUtjbp9ZokRoEIJtMdosJnKVosdwKVQ3e00ZIt2 9YyK4J3iWFSzUfNWZPxpr+8zf4Ecugg0qDSGoVj+HwNSIkKf8puK4n4raJuQB2zps8Dz wpDcTlGfIWo6oEcgZvZYa5bda0aJ8x27HPlSHQtBJFGumIum2YvRs6ZFgkgkbxSSHqC9 0X5Q== X-Forwarded-Encrypted: i=1; AJvYcCVDUVJ+gmthFW8hQhOHnVBofkkpaF9s26fCIJZf58+Jzl8desynAMK8mCMdMdejGqqmTm2IjjO80+9n@nongnu.org X-Gm-Message-State: AOJu0Yzeuj2Y1gdy5jO5wL48z7eBdcZozOaRxBUtDe9lgq1qFmZ7KF1i QYBYjF/yVXDP1+2qPTYWa/knqYzy/fuyAV5vFbJhs56R4mzVuIbuaIk8qzPHp0U= X-Google-Smtp-Source: AGHT+IEhRVcrcKwMKlNaxNSI/imjjiLopX8y/9g5Jy0FyeRiJr3xrTsHsyEHIuPGO2zgp3zcNfsrCw== X-Received: by 2002:a05:6358:2a5:b0:1b5:fde1:d00c with SMTP id e5c5f4694b2df-1b603cfccbbmr57708155d.25.1724867282621; Wed, 28 Aug 2024 10:48:02 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta , Richard Henderson Subject: [PATCH v11 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Date: Wed, 28 Aug 2024 10:47:31 -0700 Message-ID: <20240828174739.714313-14-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240828174739.714313-1-debug@rivosinc.com> References: <20240828174739.714313-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=debug@rivosinc.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1724867613425116600 Content-Type: text/plain; charset="utf-8" zicfiss protects shadow stack using new page table encodings PTE.W=3D1, PTE.R=3D0 and PTE.X=3D0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack accesses to RO memory leads to store page fault. To implement special nature of shadow stack memory where only selected stores (shadow stack stores from sspush) have to be allowed while rest of regular stores disallowed, new MMU TLB index is created for shadow stack. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 37 +++++++++++++++++++++++++++++++------ target/riscv/internals.h | 3 +++ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index be4ac3d54e..39544cade6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -893,6 +893,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, hwaddr ppn; int napot_bits =3D 0; target_ulong napot_mask; + bool is_sstack_idx =3D ((mmu_idx & MMU_IDX_SS_WRITE) =3D=3D MMU_IDX_SS= _WRITE); + bool sstack_page =3D false; =20 /* * Check if we should use the background registers for the two @@ -1101,21 +1103,36 @@ restart: return TRANSLATE_FAIL; } =20 + target_ulong rwx =3D pte & (PTE_R | PTE_W | PTE_X); /* Check for reserved combinations of RWX flags. */ - switch (pte & (PTE_R | PTE_W | PTE_X)) { - case PTE_W: + switch (rwx) { case PTE_W | PTE_X: return TRANSLATE_FAIL; + case PTE_W: + /* if bcfi enabled, PTE_W is not reserved and shadow stack page */ + if (cpu_get_bcfien(env) && first_stage) { + sstack_page =3D true; + /* if ss index, read and write allowed. else only read allowed= */ + rwx =3D is_sstack_idx ? PTE_R | PTE_W : PTE_R; + break; + } + return TRANSLATE_FAIL; + case PTE_R: + /* shadow stack writes to readonly memory are page faults */ + if (is_sstack_idx && access_type =3D=3D MMU_DATA_STORE) { + return TRANSLATE_FAIL; + } + break; } =20 int prot =3D 0; - if (pte & PTE_R) { + if (rwx & PTE_R) { prot |=3D PAGE_READ; } - if (pte & PTE_W) { + if (rwx & PTE_W) { prot |=3D PAGE_WRITE; } - if (pte & PTE_X) { + if (rwx & PTE_X) { bool mxr =3D false; =20 /* @@ -1160,7 +1177,7 @@ restart: =20 if (!((prot >> access_type) & 1)) { /* Access check failed */ - return TRANSLATE_FAIL; + return sstack_page ? TRANSLATE_PMP_FAIL : TRANSLATE_FAIL; } =20 target_ulong updated_pte =3D pte; @@ -1347,9 +1364,17 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vad= dr addr, break; case MMU_DATA_LOAD: cs->exception_index =3D RISCV_EXCP_LOAD_ADDR_MIS; + /* shadow stack mis aligned accesses are access faults */ + if (mmu_idx & MMU_IDX_SS_WRITE) { + cs->exception_index =3D RISCV_EXCP_LOAD_ACCESS_FAULT; + } break; case MMU_DATA_STORE: cs->exception_index =3D RISCV_EXCP_STORE_AMO_ADDR_MIS; + /* shadow stack mis aligned accesses are access faults */ + if (mmu_idx & MMU_IDX_SS_WRITE) { + cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } break; default: g_assert_not_reached(); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0ac17bc5ad..ddbdee885b 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -30,12 +30,15 @@ * - U+2STAGE 0b100 * - S+2STAGE 0b101 * - S+SUM+2STAGE 0b110 + * - Shadow stack+U 0b1000 + * - Shadow stack+S 0b1001 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) +#define MMU_IDX_SS_WRITE (1 << 3) =20 static inline int mmuidx_priv(int mmu_idx) { --=20 2.44.0