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Wed, 28 Aug 2024 02:52:58 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Jessica Clarke , Kyle Evans , Richard Henderson Subject: [PATCH v4 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Date: Wed, 28 Aug 2024 19:52:28 +1000 Message-Id: <20240828095243.90491-3-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828095243.90491-1-itachis@FreeBSD.org> References: <20240828095243.90491-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724838871841116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h index e17c910ae9..ba589909e2 100644 --- a/bsd-user/riscv/target_arch_cpu.h +++ b/bsd-user/riscv/target_arch_cpu.h @@ -36,4 +36,98 @@ static inline void target_cpu_init(CPURISCVState *env, env->pc =3D regs->sepc; } =20 +static inline void target_cpu_loop(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + int trapnr; + abi_long ret; + unsigned int syscall_num; + int32_t signo, code; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + signo =3D 0; + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + case RISCV_EXCP_U_ECALL: + syscall_num =3D env->gpr[xT0];=20 + env->pc +=3D TARGET_INSN_SIZE; + /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */ + if (TARGET_FREEBSD_NR___syscall =3D=3D syscall_num || + TARGET_FREEBSD_NR_syscall =3D=3D syscall_num) { + ret =3D do_freebsd_syscall(env, + env->gpr[xA0],=20 + env->gpr[xA1],=20 + env->gpr[xA2],=20 + env->gpr[xA3],=20 + env->gpr[xA4],=20 + env->gpr[xA5],=20 + env->gpr[xA6],=20 + env->gpr[xA7],=20 + 0); + } else { + ret =3D do_freebsd_syscall(env, + syscall_num, + env->gpr[xA0],=20 + env->gpr[xA1],=20 + env->gpr[xA2],=20 + env->gpr[xA3],=20 + env->gpr[xA4],=20 + env->gpr[xA5],=20 + env->gpr[xA6],=20 + env->gpr[xA7] =20 + ); + } + + /* + * Compare to cpu_set_syscall_retval() in + * riscv/riscv/vm_machdep.c + */ + if (ret >=3D 0) { + env->gpr[xA0] =3D ret;=20 + env->gpr[xT0] =3D 0; =20 + } else if (ret =3D=3D -TARGET_ERESTART) { + env->pc -=3D TARGET_INSN_SIZE; + } else if (ret !=3D -TARGET_EJUSTRETURN) { + env->gpr[xA0] =3D -ret;=20 + env->gpr[xT0] =3D 1; =20 + } + break; + case RISCV_EXCP_ILLEGAL_INST: + signo =3D TARGET_SIGILL; + code =3D TARGET_ILL_ILLOPC; + break; + case RISCV_EXCP_BREAKPOINT: + signo =3D TARGET_SIGTRAP; + code =3D TARGET_TRAP_BRKPT; + break; + case EXCP_DEBUG: + signo =3D TARGET_SIGTRAP; + code =3D TARGET_TRAP_BRKPT; + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception " + "0x%x - aborting\n", trapnr); + cpu_dump_state(cs, stderr, 0); + abort(); + } + + if (signo) { + force_sig_fault(signo, code, env->pc); + } + + process_pending_signals(env); + } +} + #endif /* TARGET_ARCH_CPU_H */ --=20 2.34.1