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Tue, 27 Aug 2024 16:19:35 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta Subject: [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk Date: Tue, 27 Aug 2024 16:19:04 -0700 Message-ID: <20240827231906.553327-21-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240827231906.553327-1-debug@rivosinc.com> References: <20240827231906.553327-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=debug@rivosinc.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1724801024977116600 Content-Type: text/plain; charset="utf-8" sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta --- disas/riscv.c | 19 ++++++++++++++++++- disas/riscv.h | 1 + 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 5eafb7f7f3..6e9ba42edd 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -980,6 +980,8 @@ typedef enum { rv_op_ssrdp =3D 949, rv_op_ssamoswap_w =3D 950, rv_op_ssamoswap_d =3D 951, + rv_op_c_sspush =3D 952, + rv_op_c_sspopchk =3D 953, } rv_op; =20 /* register names */ @@ -2244,6 +2246,10 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 }, { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, + { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush, + rv_op_sspush, 0 }, + { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk, + rv_op_sspopchk, 0 }, }; =20 /* CSR names */ @@ -2604,7 +2610,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) if (dec->cfg->ext_zcmop) { if ((((inst >> 2) & 0b111111) =3D=3D 0b100000) && (((inst >> 11) & 0b11) =3D=3D 0b0)) { - op =3D rv_c_mop_1 + ((inst >> 8) & 0b111); + unsigned int cmop_code =3D 0; + cmop_code =3D ((inst >> 8) & 0b111); + op =3D rv_c_mop_1 + cmop_code; + if (dec->cfg->ext_zicfiss) { + op =3D (cmop_code =3D=3D 0) ? rv_op_c_sspush : op; + op =3D (cmop_code =3D=3D 2) ? rv_op_c_sspopchk : o= p; + } break; } } @@ -4923,6 +4935,11 @@ static void decode_inst_operands(rv_decode *dec, rv_= isa isa) case rv_codec_lp: dec->imm =3D operand_lpl(inst); break; + case rv_codec_cmop_ss: + dec->rd =3D rv_ireg_zero; + dec->rs1 =3D dec->rs2 =3D operand_crs1(inst); + dec->imm =3D 0; + break; }; } =20 diff --git a/disas/riscv.h b/disas/riscv.h index 4895c5a301..6a3b371cd3 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -167,6 +167,7 @@ typedef enum { rv_codec_r2_imm2_imm5, rv_codec_fli, rv_codec_lp, + rv_codec_cmop_ss, } rv_codec; =20 /* structures */ --=20 2.44.0