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charset="utf-8" Add master mode tests for flexcomm i2c. Signed-off-by: Octavian Purdila --- tests/qtest/flexcomm-i2c-test.c | 169 ++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 +- 2 files changed, 170 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/flexcomm-i2c-test.c diff --git a/tests/qtest/flexcomm-i2c-test.c b/tests/qtest/flexcomm-i2c-tes= t.c new file mode 100644 index 0000000000..30ab40e132 --- /dev/null +++ b/tests/qtest/flexcomm-i2c-test.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2024 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "qemu/config-file.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qemu/sockets.h" +#include "sysemu/sysemu.h" +#include "qemu/main-loop.h" +#include "qemu/option.h" +#include "exec/memory.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-core.h" + +#include "hw/i2c/flexcomm_i2c.h" +#include "hw/arm/svd/rt500.h" +#include "hw/misc/i2c_tester.h" +#include "reg-utils.h" + +#define PERIPH_ADDR (0x50) +#define INVALID_ADDR (0x10) + +#define REG_ADDR 11 +#define REG_VALUE 0xAA + +#define FLEXCOMM_BASE RT500_FLEXCOMM0_BASE +#define FLEXCOMM_I2C_BASE RT500_FLEXCOMM0_BASE +#define DEVICE_NAME "/machine/soc/flexcomm0" + +struct TestState { + QTestState *qtest; +}; + +static void master_test(gconstpointer user_data) +{ + struct TestState *t =3D (struct TestState *)user_data; + uint32_t tmp; + + qtest_irq_intercept_out_named(t->qtest, DEVICE_NAME, + SYSBUS_DEVICE_GPIO_IRQ); + + /* Select and lock I2C */ + tmp =3D FLEXCOMM_PERSEL_I2C; + FIELD_DP32(tmp, FLEXCOMM_PSELID, LOCK, 1); + REG32_WRITE(FLEXCOMM, PSELID, tmp); + + /* Enable master mode */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, CFG, MSTEN, 1); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, CFG, MSTEN) =3D=3D 1); + + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTPENDING) =3D=3D 1); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_IDLE); + + /* Enable interrupts */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, INTENSET, MSTPENDINGEN, 1); + g_assert_true(get_irq(0)); + + /* start for invalid address */ + REG32_WRITE(FLEXCOMM_I2C, MSTDAT, INVALID_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_NAKADR); + g_assert_true(get_irq(0)); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* write past the last register */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, PERIPH_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, I2C_TESTER_NUM_REGS + 10= ); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_NAKDAT); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* write value to register */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, PERIPH_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, REG_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, REG_VALUE); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_IDLE); + + /* read value back from register */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, PERIPH_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, REG_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTCONTINUE, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_TXRDY); + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, (PERIPH_ADDR + 1)); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + g_assert_true(get_irq(0)); + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_RXRDY); + g_assert_cmpuint(REG32_READ_FIELD(FLEXCOMM_I2C, MSTDAT, DATA), =3D=3D, + REG_VALUE); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* + * Check that the master ended the transaction (i.e. i2c_end_transfer = was + * called). If the master does not properly end the transaction this w= ould + * be seen as a restart and it would not be NACKed. + */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, MSTDAT, DATA, INVALID_ADDR); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTART, 1); + + g_assert(REG32_READ_FIELD(FLEXCOMM_I2C, STAT, MSTSTATE) =3D=3D + MSTSTATE_NAKADR); + g_assert_true(get_irq(0)); + REG32_WRITE_FIELD_NOUPDATE(FLEXCOMM_I2C, MSTCTL, MSTSTOP, 1); + + /* Disable interrupts */ + REG32_WRITE_FIELD(FLEXCOMM_I2C, INTENCLR, MSTPENDINGCLR, 1); + g_assert_false(get_irq(0)); +} + +int main(int argc, char **argv) +{ + int ret; + struct TestState test; + + module_call_init(MODULE_INIT_QOM); + g_test_init(&argc, &argv, NULL); + + qtest_add_data_func("/flexcomm-i2c/master", &test, master_test); + + test.qtest =3D qtest_start("-M rt595-evk " + "-device i2c-tester,address=3D0x50,bus=3D/flexco= mm0/i2c"); + ret =3D g_test_run(); + qtest_end(); + + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 93d1f781bc..df69c1cfbf 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -229,7 +229,7 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-= test'] : []) + \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ - (config_all_devices.has_key('CONFIG_FLEXCOMM') ? ['flexcomm-test', 'flex= comm-usart-test'] : []) + \ + (config_all_devices.has_key('CONFIG_FLEXCOMM') ? ['flexcomm-test', 'flex= comm-usart-test', 'flexcomm-i2c-test'] : []) + \ ['arm-cpu-features', 'boot-serial-test'] =20 --=20 2.46.0.295.g3b9ea8a38a-goog