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([50.37.200.153]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-203855dd269sm74503625ad.135.2024.08.26.20.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 20:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; t=1724730650; x=1725335450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S0zsQlf6Fpb3LogkSdeHLWACnHhbNDLVL/P8RxdypHM=; b=emOTH1OSvNprDeGur9l+DepiM4vZ7VkUVv5X63f73hsn/eErEjxDNdRYOwhIywBIEc 5aeDabqQbpjUkSSyoz2rSyOYpwc6ePpEjRpkkFZAQvIiJCsHOXqJ1Si7zwOy/dmVdWMU Jt2bcM+feFoOec+1LbFkouMrJL6WWHKQaqrrg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724730650; x=1725335450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S0zsQlf6Fpb3LogkSdeHLWACnHhbNDLVL/P8RxdypHM=; b=Dzotwy4DUp9BXTpGkTrdmogXbP8nHeSRdP0KhcJuUMQ0s9IHjDHCLjTJEfVqgcouk4 9xJ4jtlNRwtqWIDrRU+wzPfoDLHinNao4hdTjp63iLFOll4LF/3MaKw68Oi/KwPRDUSc UmIkqoZ6grlruX0rgXmND+/8opEGMOgNH8mFc1ktSqzegTdPFW6PZHioPytAh2WYjqKC Z85NTYf+DIo072m4SB9mDCRycz5XEAxKuz25hUGFAUtjQlrIqhS85LLrj1YTmUuftiVR sqJMSzbOFr6ysSqnCK4TSHLI8Yj9T8TWQLnXXjzKK6hO4lVJYdlOYLcUTz2tTTLH/5Ok KRcQ== X-Forwarded-Encrypted: i=1; AJvYcCWIWSzuAN1V12lOnzC3H97RAjjLXa6RMcla0HG2tkcahq/kKkuVzVn6iFa0DnSgF/aI9vPJwXa+ik8s@nongnu.org X-Gm-Message-State: AOJu0YwmpLgmcWllxE2N03grMJgL4cyZK+HLlfNHbKfiFwEhD9IX755f Zx0yBXB1YRbz3+Tlh3AIYrQ0qGwvqUZA9ibnIviXLNqjcDfnNIWz76nJEt3L+lo= X-Google-Smtp-Source: AGHT+IEwuUQ3gLat4m6or9KyVLa/RrfyK5pIfIYJe9KC8cESOTG7v7uh7oE0g8/jcAIfTVwoHF6kEQ== X-Received: by 2002:a17:903:2c7:b0:201:f1b5:24ac with SMTP id d9443c01a7336-2039e51279bmr139896365ad.54.1724730650264; Mon, 26 Aug 2024 20:50:50 -0700 (PDT) From: Doug Brown To: Francisco Iglesias , Pavel Pisa Cc: Jason Wang , Paolo Bonzini , qemu-devel@nongnu.org, Doug Brown Subject: [PATCH v2 4/7] hw/net/can/xlnx-versal-canfd: Handle flags correctly Date: Mon, 26 Aug 2024 20:49:24 -0700 Message-Id: <20240827034927.66659-5-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240827034927.66659-1-doug@schmorgal.com> References: <20240827034927.66659-1-doug@schmorgal.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=doug@schmorgal.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @schmorgal.com) X-ZM-MESSAGEID: 1724730731829116600 Content-Type: text/plain; charset="utf-8" Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and ensure frame->flags is always initialized to 0. Note that the Xilinx IP core doesn't allow manually setting the ESI bit during transmits, so it's only implemented for the receive case. Signed-off-by: Doug Brown Reviewed-by: Pavel Pisa --- hw/net/can/xlnx-versal-canfd.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c index 1704b558d0..47631917ab 100644 --- a/hw/net/can/xlnx-versal-canfd.c +++ b/hw/net/can/xlnx-versal-canfd.c @@ -872,6 +872,8 @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_ca= n_frame *frame, uint32_t id_reg_val =3D 0; bool is_rtr =3D false; =20 + frame->flags =3D 0; + /* Check that reg_num should be within TX register space. */ assert(reg_num <=3D R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * s->cfg.tx_fifo)); @@ -913,7 +915,7 @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_ca= n_frame *frame, * 15 49 - 64 */ =20 - frame->flags =3D QEMU_CAN_FRMF_TYPE_FD; + frame->flags |=3D QEMU_CAN_FRMF_TYPE_FD; =20 if (dlc_value < 8) { frame->can_dlc =3D dlc_value; @@ -921,6 +923,10 @@ static void regs2frame(XlnxVersalCANFDState *s, qemu_c= an_frame *frame, assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array)); frame->can_dlc =3D canfd_dlc_array[dlc_value - 8]; } + + if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) { + frame->flags |=3D QEMU_CAN_FRMF_BRS; + } } else { /* * FD Format bit not set that means it is a CAN Frame. @@ -1058,6 +1064,13 @@ static void store_rx_sequential(XlnxVersalCANFDState= *s, dlc_reg_val =3D FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 = + i); } } + + if (frame->flags & QEMU_CAN_FRMF_BRS) { + dlc_reg_val |=3D FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); + } + if (frame->flags & QEMU_CAN_FRMF_ESI) { + dlc_reg_val |=3D FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1); + } } else { is_canfd_frame =3D false; =20 --=20 2.34.1