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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757903932116600 From: Paolo Bonzini This is needed for Rust support. Signed-off-by: Paolo Bonzini --- meson.build | 2 +- python/scripts/vendor.py | 4 ++-- python/wheels/meson-1.2.3-py3-none-any.whl | Bin 964928 -> 0 bytes python/wheels/meson-1.5.0-py3-none-any.whl | Bin 0 -> 959846 bytes pythondeps.toml | 2 +- tests/lcitool/mappings.yml | 2 +- 6 files changed, 5 insertions(+), 5 deletions(-) diff --git a/meson.build b/meson.build index 81ecd4bae7..7eb4b8a41c 100644 --- a/meson.build +++ b/meson.build @@ -1,4 +1,4 @@ -project('qemu', ['c'], meson_version: '>=3D1.1.0', +project('qemu', ['c'], meson_version: '>=3D1.5.0', default_options: ['warning_level=3D1', 'c_std=3Dgnu11', 'cpp_std= =3Dgnu++11', 'b_colorout=3Dauto', 'b_staticpic=3Dfalse', 'stdsplit=3Dfalse', 'opti= mization=3D2', 'b_pie=3Dtrue'], version: files('VERSION')) diff --git a/python/scripts/vendor.py b/python/scripts/vendor.py index 07aff97cca..0405e910b4 100755 --- a/python/scripts/vendor.py +++ b/python/scripts/vendor.py @@ -41,8 +41,8 @@ def main() -> int: parser.parse_args() =20 packages =3D { - "meson=3D=3D1.2.3": - "4533a43c34548edd1f63a276a42690fce15bde9409bcf20c4b8fa3d7e4d7cac1", + "meson=3D=3D1.5.0": + "52b34f4903b882df52ad0d533146d4b992c018ea77399f825579737672ae7b20", } =20 vendor_dir =3D Path(__file__, "..", "..", "wheels").resolve() diff --git a/python/wheels/meson-1.2.3-py3-none-any.whl b/python/wheels/mes= on-1.2.3-py3-none-any.whl deleted file mode 100644 index a8b84e5f11..0000000000 Binary files a/python/wheels/meson-1.2.3-py3-none-any.whl and /dev/null dif= fer diff --git a/python/wheels/meson-1.5.0-py3-none-any.whl b/python/wheels/mes= on-1.5.0-py3-none-any.whl new file mode 100644 index 0000000000..c7edeb37ad Binary files /dev/null and b/python/wheels/meson-1.5.0-py3-none-any.whl dif= fer diff --git a/pythondeps.toml b/pythondeps.toml index f6e590fdd8..a1c6ca9662 100644 --- a/pythondeps.toml +++ b/pythondeps.toml @@ -19,7 +19,7 @@ =20 [meson] # The install key should match the version in python/wheels/ -meson =3D { accepted =3D ">=3D1.1.0", installed =3D "1.2.3", canary =3D "m= eson" } +meson =3D { accepted =3D ">=3D1.5.0", installed =3D "1.5.0", canary =3D "m= eson" } =20 [docs] # Please keep the installed versions in sync with docs/requirements.txt diff --git a/tests/lcitool/mappings.yml b/tests/lcitool/mappings.yml index 03b974ad02..9721016e0d 100644 --- a/tests/lcitool/mappings.yml +++ b/tests/lcitool/mappings.yml @@ -63,7 +63,7 @@ mappings: pypi_mappings: # Request more recent version meson: - default: meson=3D=3D0.63.2 + default: meson=3D=3D1.5.0 =20 # Drop packages that need devel headers python3-numpy: --=20 2.45.2 From nobody Sun Nov 24 07:49:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1724757853; cv=none; d=zohomail.com; s=zohoarc; b=LVgjjRJnqsydn//ueW6qcA8sKsYe5mQFM7zS7s/aLerjahSas0aP1JIp522pkFjhuQqG+gVTAuSasQg6l2kykbNpGNapMLcgCzoBJewGsdOemZxS3T8WwutZAM1pGe9Zr3jzPcjbLNWzweR4+2VdjazllfIC21y0Qzh6tf8NPgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724757853; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VBrGB2rIabK5bRnXDdQUAS0ChrK3HI/3tgD35y925mM=; b=eA3e5sEAV+D5FVioqBIvkQMy4hw4ksVNPzooqgY03xCJTWKkLOwgquSRhDAVqdXGFE5zd1nNDM2hPAMBhvJDHnabjsRhBtIdsZ/ZjMuhZWbcPeaPmc9pBnfZ8SHYmUMdmMDjhpFT/0yJ7hzBkE8T/BeG4KbliNgggvVmOrSW3mo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724757853729849.4811296544702; Tue, 27 Aug 2024 04:24:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1siuIh-0002aT-AY; Tue, 27 Aug 2024 07:23:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1siuIc-0002Mr-1M for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:23:47 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1siuIa-0000i5-45 for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:23:45 -0400 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5bf0261f162so6401670a12.0 for ; Tue, 27 Aug 2024 04:23:43 -0700 (PDT) Received: from [127.0.1.1] (adsl-242.37.6.163.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757856071116600 Add rust feature in meson.build, configure, to prepare for adding Rust code in the followup commits. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 +++++ meson.build | 25 ++++++++++++++++++++++++- Kconfig | 1 + Kconfig.host | 3 +++ meson_options.txt | 3 +++ rust/Kconfig | 0 scripts/meson-buildoptions.sh | 3 +++ 7 files changed, 39 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3584d6a6c6..0bc8e515da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4243,6 +4243,11 @@ F: docs/sphinx/ F: docs/_templates/ F: docs/devel/docs.rst =20 +Rust build system integration +M: Manos Pitsidianakis +S: Maintained +F: rust/Kconfig + Miscellaneous ------------- Performance Tools and Tests diff --git a/meson.build b/meson.build index 7eb4b8a41c..67eb4eda64 100644 --- a/meson.build +++ b/meson.build @@ -70,6 +70,22 @@ if host_os =3D=3D 'darwin' and \ all_languages +=3D ['objc'] objc =3D meson.get_compiler('objc') endif +if get_option('rust').enabled() and meson.version().version_compare('<1.0.= 0') + error('Rust support requires Meson version >=3D1.0.0') +endif +have_rust =3D false +if not get_option('rust').disabled() and add_languages('rust', required: g= et_option('rust'), native: false) + rustc =3D meson.get_compiler('rust') + have_rust =3D true + if rustc.version().version_compare('<1.80.0') + if get_option('rust').enabled() + error('rustc version ' + rustc.version() + ' is unsupported: Please = upgrade to at least 1.80.0') + else + warning('rustc version ' + rustc.version() + ' is unsupported: Disab= ling Rust compilation. Please upgrade to at least 1.80.0 to use Rust.') + have_rust =3D false + endif + endif +endif =20 dtrace =3D not_found stap =3D not_found @@ -2131,6 +2147,7 @@ endif =20 config_host_data =3D configuration_data() =20 +config_host_data.set('CONFIG_HAVE_RUST', have_rust) audio_drivers_selected =3D [] if have_system audio_drivers_available =3D { @@ -3076,7 +3093,8 @@ host_kconfig =3D \ (host_os =3D=3D 'linux' ? ['CONFIG_LINUX=3Dy'] : []) + \ (multiprocess_allowed ? ['CONFIG_MULTIPROCESS_ALLOWED=3Dy'] : []) + \ (vfio_user_server_allowed ? ['CONFIG_VFIO_USER_SERVER_ALLOWED=3Dy'] : []= ) + \ - (hv_balloon ? ['CONFIG_HV_BALLOON_POSSIBLE=3Dy'] : []) + (hv_balloon ? ['CONFIG_HV_BALLOON_POSSIBLE=3Dy'] : []) + \ + (have_rust ? ['CONFIG_HAVE_RUST=3Dy'] : []) =20 ignored =3D [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR', 'TARGET_ARCH' ] =20 @@ -4287,6 +4305,11 @@ if 'objc' in all_languages else summary_info +=3D {'Objective-C compiler': false} endif +summary_info +=3D {'Rust support': have_rust} +if have_rust + summary_info +=3D {'rustc version': rustc.version()} + summary_info +=3D {'rustc': ' '.join(rustc.cmd_array())} +endif option_cflags =3D (get_option('debug') ? ['-g'] : []) if get_option('optimization') !=3D 'plain' option_cflags +=3D ['-O' + get_option('optimization')] diff --git a/Kconfig b/Kconfig index fb6a24a2de..63ca7f46df 100644 --- a/Kconfig +++ b/Kconfig @@ -4,3 +4,4 @@ source accel/Kconfig source target/Kconfig source hw/Kconfig source semihosting/Kconfig +source rust/Kconfig diff --git a/Kconfig.host b/Kconfig.host index 17f405004b..4ade7899d6 100644 --- a/Kconfig.host +++ b/Kconfig.host @@ -52,3 +52,6 @@ config VFIO_USER_SERVER_ALLOWED =20 config HV_BALLOON_POSSIBLE bool + +config HAVE_RUST + bool diff --git a/meson_options.txt b/meson_options.txt index 0269fa0f16..fa94a5ce97 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -371,3 +371,6 @@ option('hexagon_idef_parser', type : 'boolean', value := true, =20 option('x86_version', type : 'combo', choices : ['0', '1', '2', '3', '4'],= value: '1', description: 'tweak required x86_64 architecture version beyond com= piler default') + +option('rust', type: 'feature', value: 'auto', + description: 'Rust support') diff --git a/rust/Kconfig b/rust/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index c97079a38c..5e8a225a6b 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -170,6 +170,7 @@ meson_options_help() { printf "%s\n" ' rbd Ceph block device driver' printf "%s\n" ' rdma Enable RDMA-based migration' printf "%s\n" ' replication replication support' + printf "%s\n" ' rust Rust support' printf "%s\n" ' rutabaga-gfx rutabaga_gfx support' printf "%s\n" ' sdl SDL user interface' printf "%s\n" ' sdl-image SDL Image support for icons' @@ -452,6 +453,8 @@ _meson_option_parse() { --disable-replication) printf "%s" -Dreplication=3Ddisabled ;; --enable-rng-none) printf "%s" -Drng_none=3Dtrue ;; --disable-rng-none) printf "%s" -Drng_none=3Dfalse ;; + --enable-rust) printf "%s" -Drust=3Denabled ;; + --disable-rust) printf "%s" -Drust=3Ddisabled ;; --enable-rutabaga-gfx) printf "%s" -Drutabaga_gfx=3Denabled ;; --disable-rutabaga-gfx) printf "%s" -Drutabaga_gfx=3Ddisabled ;; --enable-safe-stack) printf "%s" -Dsafe_stack=3Dtrue ;; --=20 2.45.2 From nobody Sun Nov 24 07:49:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1724757861; cv=none; d=zohomail.com; s=zohoarc; b=Nsge3v5uS/1GXoVpuzvF2CescfHkO8lCyCXWqkx3jARL0dj4WQwC+8ljboH4rqF64aBuFaLDSlGa/CuXnUtdo0M9wsQxgjgxWxpI54kD2cQtnOrd6rdIBWagyhYfHf7ykw0B/2z0uzA6dBCADQD266gFct0DZKqdKpL9u1gZADo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724757861; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ejIq34eU8g4lAxI8GBYvWXzFq8igCRIQX1rzGEt4Sjo=; b=RzZFdnu2+hwOyNajTNlf+fopoP1EoZ/HI+sWAqv14WDlxiKlxdfO9pZ3s3FNq1zOqL2X0LkWlGiEWOBIYmjVnntO3+rTdrw5Y/R3/XzkxPKP2LduVCoHSwVcKqMuegncC112ipzLTvgwuXkD9kqv/RRmIW0sq14aTjjhuipMNS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724757861723718.0618255665423; Tue, 27 Aug 2024 04:24:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1siuIl-0002gl-GP; Tue, 27 Aug 2024 07:23:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1siuId-0002UC-Rp for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:23:48 -0400 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1siuIb-0000iS-PX for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:23:47 -0400 Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-53349d3071eso6501600e87.2 for ; Tue, 27 Aug 2024 04:23:45 -0700 (PDT) Received: from [127.0.1.1] (adsl-242.37.6.163.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757864227116600 From: Paolo Bonzini Include the correct path and arguments to rustc in the native and cross files (native compilation is needed for procedural macros). Signed-off-by: Paolo Bonzini --- configure | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-- meson.build | 8 +++----- 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/configure b/configure index 019fcbd0ef..9ef6005c55 100755 --- a/configure +++ b/configure @@ -207,6 +207,8 @@ for opt do ;; --objcc=3D*) objcc=3D"$optarg" ;; + --rustc=3D*) RUSTC=3D"$optarg" + ;; --cpu=3D*) cpu=3D"$optarg" ;; --extra-cflags=3D*) @@ -252,6 +254,9 @@ python=3D download=3D"enabled" skip_meson=3Dno use_containers=3D"yes" +# do not enable by default because cross compilation requires --rust-targe= t-triple +rust=3D"disabled" +rust_target_triple=3D"" gdb_bin=3D$(command -v "gdb-multiarch" || command -v "gdb") gdb_arches=3D"" =20 @@ -317,6 +322,8 @@ windmc=3D"${WINDMC-${cross_prefix}windmc}" pkg_config=3D"${PKG_CONFIG-${cross_prefix}pkg-config}" sdl2_config=3D"${SDL2_CONFIG-${cross_prefix}sdl2-config}" =20 +rustc=3D"${RUSTC-rustc}" + check_define() { cat > $TMPC < "${TMPDIR1}/= ${TMPB}.out"; then + rust_host_triple=3D$(sed -n 's/^host: //p' "${TMPDIR1}/${TMPB}.out") +else + if test "$rust" =3D enabled; then + error_exit "could not execute rustc binary \"$rustc\"" + fi + rust=3Ddisabled +fi +if test "$rust" !=3D disabled && test -z "$rust_target_triple"; then + rust_target_triple=3D$rust_host_triple +fi + +########################################## # functions to probe cross compilers =20 container=3D"no" @@ -1604,6 +1636,9 @@ if test "$container" !=3D no; then echo "RUNC=3D$runc" >> $config_host_mak fi echo "SUBDIRS=3D$subdirs" >> $config_host_mak +if test "$rust" !=3D disabled; then + echo "RUST_TARGET_TRIPLE=3D$rust_target_triple" >> $config_host_mak +fi echo "PYTHON=3D$python" >> $config_host_mak echo "MKVENV_ENSUREGROUP=3D$mkvenv ensuregroup $mkvenv_online_flag" >> $co= nfig_host_mak echo "GENISOIMAGE=3D$genisoimage" >> $config_host_mak @@ -1735,6 +1770,13 @@ if test "$skip_meson" =3D no; then echo "c =3D [$(meson_quote $cc $CPU_CFLAGS)]" >> $cross test -n "$cxx" && echo "cpp =3D [$(meson_quote $cxx $CPU_CFLAGS)]" >> $c= ross test -n "$objcc" && echo "objc =3D [$(meson_quote $objcc $CPU_CFLAGS)]" = >> $cross + if test "$rust" !=3D disabled; then + if test "$rust_host_triple" !=3D "$rust_target_triple"; then + echo "rust =3D [$(meson_quote $rustc --target "$rust_target_triple")= ]" >> $cross + else + echo "rust =3D [$(meson_quote $rustc)]" >> $cross + fi + fi echo "ar =3D [$(meson_quote $ar)]" >> $cross echo "dlltool =3D [$(meson_quote $dlltool)]" >> $cross echo "nm =3D [$(meson_quote $nm)]" >> $cross @@ -1770,6 +1812,9 @@ if test "$skip_meson" =3D no; then echo "# Automatically generated by configure - do not modify" > $native echo "[binaries]" >> $native echo "c =3D [$(meson_quote $host_cc)]" >> $native + if test "$rust" !=3D disabled; then + echo "rust =3D [$(meson_quote $rustc)]" >> $cross + fi mv $native config-meson.native meson_option_add --native-file meson_option_add config-meson.native @@ -1788,6 +1833,7 @@ if test "$skip_meson" =3D no; then test "$pie" =3D no && meson_option_add -Db_pie=3Dfalse =20 # QEMU options + test "$rust" !=3D "auto" && meson_option_add "-Drust=3D$rust" test "$cfi" !=3D false && meson_option_add "-Dcfi=3D$cfi" "-Db_lto=3D$cf= i" test "$docs" !=3D auto && meson_option_add "-Ddocs=3D$docs" test -n "${LIB_FUZZING_ENGINE+xxx}" && meson_option_add "-Dfuzzing_engin= e=3D$LIB_FUZZING_ENGINE" diff --git a/meson.build b/meson.build index 67eb4eda64..065739ccb7 100644 --- a/meson.build +++ b/meson.build @@ -70,9 +70,6 @@ if host_os =3D=3D 'darwin' and \ all_languages +=3D ['objc'] objc =3D meson.get_compiler('objc') endif -if get_option('rust').enabled() and meson.version().version_compare('<1.0.= 0') - error('Rust support requires Meson version >=3D1.0.0') -endif have_rust =3D false if not get_option('rust').disabled() and add_languages('rust', required: g= et_option('rust'), native: false) rustc =3D meson.get_compiler('rust') @@ -4307,8 +4304,9 @@ else endif summary_info +=3D {'Rust support': have_rust} if have_rust - summary_info +=3D {'rustc version': rustc.version()} - summary_info +=3D {'rustc': ' '.join(rustc.cmd_array())} + summary_info +=3D {'rustc version': rustc.version()} + summary_info +=3D {'rustc': ' '.join(rustc.cmd_array())} + summary_info +=3D {'Rust target': config_host['RUST_TARGET_TRIPLE']} endif option_cflags =3D (get_option('debug') ? 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757890073116600 Add bindings_rs target for generating rust bindings to target-independent qemu C APIs. The bindings need be created before any rust crate that uses them is compiled. The bindings.rs file will end up in BUILDDIR/bindings.rs and have the same name as a target: ninja bindings.rs Signed-off-by: Paolo Bonzini Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 4 +++ meson.build | 34 +++++++++++++++++++ rust/wrapper.h | 39 +++++++++++++++++++++ rust/.gitignore | 3 ++ rust/meson.build | 0 scripts/rust/rustc_args.py | 84 ++++++++++++++++++++++++++++++++++++++++++= ++++ 6 files changed, 164 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0bc8e515da..642c07a9ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4246,7 +4246,11 @@ F: docs/devel/docs.rst Rust build system integration M: Manos Pitsidianakis S: Maintained +F: scripts/rust/ +F: rust/.gitignore F: rust/Kconfig +F: rust/meson.build +F: rust/wrapper.h =20 Miscellaneous ------------- diff --git a/meson.build b/meson.build index 065739ccb7..05446acbc6 100644 --- a/meson.build +++ b/meson.build @@ -3871,6 +3871,40 @@ common_all =3D static_library('common', implicit_include_directories: false, dependencies: common_ss.all_dependencies()) =20 +if have_rust and have_system + rustc_config_args =3D run_command( + find_program('scripts/rust/rustc_args.py'), + '--config-headers', meson.project_build_root() / 'config-host.h', + capture : true, + check: true).stdout().strip().split() + + bindings_rs =3D import('rust').bindgen( + input: 'rust/wrapper.h', + dependencies: common_ss.all_dependencies(), + output: 'bindings.rs', + include_directories: include_directories('.', 'include'), + bindgen_version: ['>=3D0.69.4'], + args: [ + '--disable-header-comment', + '--raw-line', '// @generated', + '--ctypes-prefix', 'core::ffi', + '--formatter', 'rustfmt', + '--generate-block', + '--generate-cstr', + '--impl-debug', + '--merge-extern-blocks', + '--no-doc-comments', + '--use-core', + '--with-derive-default', + '--allowlist-file', meson.project_source_root() + '/include/.*', + '--allowlist-file', meson.project_source_root() + '/.*', + '--allowlist-file', meson.project_build_root() + '/.*' + ], + ) + subdir('rust') +endif + + feature_to_c =3D find_program('scripts/feature_to_c.py') =20 if host_os =3D=3D 'darwin' diff --git a/rust/wrapper.h b/rust/wrapper.h new file mode 100644 index 0000000000..51985f0ef1 --- /dev/null +++ b/rust/wrapper.h @@ -0,0 +1,39 @@ +/* + * QEMU System Emulator + * + * Copyright 2024 Manos Pitsidianakis + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "qemu-io.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "exec/memory.h" +#include "chardev/char-fe.h" +#include "hw/clock.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "hw/irq.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "chardev/char-serial.h" diff --git a/rust/.gitignore b/rust/.gitignore new file mode 100644 index 0000000000..1bf71b1f68 --- /dev/null +++ b/rust/.gitignore @@ -0,0 +1,3 @@ +# Ignore any cargo development build artifacts; for qemu-wide builds, all = build +# artifacts will go to the meson build directory. +target diff --git a/rust/meson.build b/rust/meson.build new file mode 100644 index 0000000000..e69de29bb2 diff --git a/scripts/rust/rustc_args.py b/scripts/rust/rustc_args.py new file mode 100644 index 0000000000..e4cc9720e1 --- /dev/null +++ b/scripts/rust/rustc_args.py @@ -0,0 +1,84 @@ +#!/usr/bin/env python3 + +"""Generate rustc arguments for meson rust builds. + +This program generates --cfg compile flags for the configuration headers p= assed +as arguments. + +Copyright (c) 2024 Linaro Ltd. + +Authors: + Manos Pitsidianakis + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +""" + +import argparse +import logging + +from typing import List + + +def generate_cfg_flags(header: str) -> List[str]: + """Converts defines from config[..].h headers to rustc --cfg flags.""" + + def cfg_name(name: str) -> str: + """Filter function for C #defines""" + if ( + name.startswith("CONFIG_") + or name.startswith("TARGET_") + or name.startswith("HAVE_") + ): + return name + return "" + + with open(header, encoding=3D"utf-8") as cfg: + config =3D [l.split()[1:] for l in cfg if l.startswith("#define")] + + cfg_list =3D [] + for cfg in config: + name =3D cfg_name(cfg[0]) + if not name: + continue + if len(cfg) >=3D 2 and cfg[1] !=3D "1": + continue + cfg_list.append("--cfg") + cfg_list.append(name) + return cfg_list + + +def main() -> None: + # pylint: disable=3Dmissing-function-docstring + parser =3D argparse.ArgumentParser() + parser.add_argument("-v", "--verbose", action=3D"store_true") + parser.add_argument( + "--config-headers", + metavar=3D"CONFIG_HEADER", + action=3D"append", + dest=3D"config_headers", + help=3D"paths to any configuration C headers (*.h files), if any", + required=3DFalse, + default=3D[], + ) + args =3D parser.parse_args() + if args.verbose: + logging.basicConfig(level=3Dlogging.DEBUG) + logging.debug("args: %s", args) + for header in args.config_headers: + for tok in generate_cfg_flags(header): + print(tok) + + +if __name__ =3D=3D "__main__": + main() --=20 2.45.2 From nobody Sun Nov 24 07:49:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1724757932; cv=none; d=zohomail.com; s=zohoarc; b=liI5RplWVlrVzhl9K4qpbbZZhSWLVFuyBzZJHLSEza/7HawWe4TLmeultEqpAbVXOkjXyTp3yNYEC1dUzu6O1fsi79YDN/bJ4v3Qh5yloL9fc2gTh/YraDGG/7bU7bxkPvT+pBQUbA05iUuDizAnMblDMsTOMO3U9GsEdIR3Kn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724757932; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9YXcnKmZZZbUSRgrSbJVZ31pesRUIn2Cw54Q9JgSGWk=; b=NFs/24cIKfj2ZnbKFL04+3vkHr001KCe/f9Pl/Zmp3ByslTEeav231z6aEgy0dxDj2lb29C75kLszfrsD9EGEl06vqg3Z9EDtxxmc6vzQCoCK8dK3OiQxyZMKbAVUr6gj2Y1O1eDAhCdFWOPwzaAat48WY4jeR3lAziaAlLQslU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724757931984541.5353245317407; Tue, 27 Aug 2024 04:25:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1siuIo-0002to-Op; Tue, 27 Aug 2024 07:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1siuIj-0002dI-I4 for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:23:54 -0400 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1siuIh-0000js-Qz for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:23:53 -0400 Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2f3edb2d908so56098221fa.2 for ; Tue, 27 Aug 2024 04:23:51 -0700 (PDT) Received: from [127.0.1.1] (adsl-242.37.6.163.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757944095116600 Rust crates, introduced from the next commit onwards, use the glib allocator API and need to know whether g_aligned_alloc etc are available. This commit adds a define in config_host_data that depends on glib version >=3D 2.72. Signed-off-by: Manos Pitsidianakis --- meson.build | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/meson.build b/meson.build index 05446acbc6..7f05466d12 100644 --- a/meson.build +++ b/meson.build @@ -979,6 +979,9 @@ glib =3D declare_dependency(dependencies: [glib_pc, gmo= dule], # TODO: remove this check and the corresponding workaround (qtree) when # the minimum supported glib is >=3D 2.75.3 glib_has_gslice =3D glib.version().version_compare('<2.75.3') +# Check whether glib has the aligned_alloc family of functions. +# +glib_has_aligned_alloc =3D glib.version().version_compare('>=3D2.72.0') =20 # override glib dep to include the above refinements meson.override_dependency('glib-2.0', glib) @@ -2508,6 +2511,7 @@ config_host_data.set('CONFIG_TIMERFD', cc.has_functio= n('timerfd_create')) config_host_data.set('HAVE_COPY_FILE_RANGE', cc.has_function('copy_file_ra= nge')) config_host_data.set('HAVE_GETIFADDRS', cc.has_function('getifaddrs')) config_host_data.set('HAVE_GLIB_WITH_SLICE_ALLOCATOR', glib_has_gslice) +config_host_data.set('HAVE_GLIB_WITH_ALIGNED_ALLOC', glib_has_aligned_allo= c) config_host_data.set('HAVE_OPENPTY', cc.has_function('openpty', dependenci= es: util)) config_host_data.set('HAVE_STRCHRNUL', cc.has_function('strchrnul')) config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', pre= fix: '#include ')) --=20 2.45.2 From nobody Sun Nov 24 07:49:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1724757945; cv=none; d=zohomail.com; s=zohoarc; b=j5AwUWk9Ew+2P61DM2WwLSt4Pg9PZq0E301IRkXJMozCIuj2nDBMR7rG5/VLklsBArx87uod7XYzBKnnAhom7rJZStoCkoLFboGh/TjVaa859eJdhxDZAU436tLJMIfhmrkQ2rLemS4Q5ikQNyUpYalYgO/dbN9DHKKgmd18JC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724757945; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ohqu+It40QRHzc//RGQ9VAfV//MOlOSNKWa9txWnvI0=; b=DQEVdThwVrIE9OB0rsh1JYgIIx/1WVKIPtxxIeMV7CJZ0JRF2Dvy73whNIKImk20T0Rnh4ungn/b/OVy2BtoZu3ZMtsTVyLwtDLXO19AVJWI6xyeZre6KufATzAsEU/NxKUPZJa6N5DLgKBzgGyXuRlVt0l62wvF3wL91Os+u4o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724757945014537.8920110796342; Tue, 27 Aug 2024 04:25:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1siuIs-00038j-DS; Tue, 27 Aug 2024 07:24:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1siuIq-0002zt-8x for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:24:00 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1siuIm-0000kv-KY for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:24:00 -0400 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-5a10835487fso8016119a12.1 for ; Tue, 27 Aug 2024 04:23:56 -0700 (PDT) Received: from [127.0.1.1] (adsl-242.37.6.163.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757946089116600 Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and provides some declaration macros for symbols visible to the rest of QEMU. Co-authored-by: Junjie Mao Co-authored-by: Paolo Bonzini Signed-off-by: Junjie Mao Signed-off-by: Paolo Bonzini Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 6 ++ rust/meson.build | 1 + rust/qemu-api/.gitignore | 2 + rust/qemu-api/Cargo.lock | 7 ++ rust/qemu-api/Cargo.toml | 26 +++++++ rust/qemu-api/README.md | 17 +++++ rust/qemu-api/build.rs | 14 ++++ rust/qemu-api/meson.build | 21 ++++++ rust/qemu-api/src/definitions.rs | 109 +++++++++++++++++++++++++++ rust/qemu-api/src/device_class.rs | 128 +++++++++++++++++++++++++++++++ rust/qemu-api/src/lib.rs | 154 ++++++++++++++++++++++++++++++++++= ++++ rust/qemu-api/src/tests.rs | 49 ++++++++++++ rust/rustfmt.toml | 7 ++ 13 files changed, 541 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 642c07a9ff..d35e9f6b20 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3348,6 +3348,12 @@ F: hw/core/register.c F: include/hw/register.h F: include/hw/registerfields.h =20 +Rust +M: Manos Pitsidianakis +S: Maintained +F: rust/qemu-api +F: rust/rustfmt.toml + SLIRP M: Samuel Thibault S: Maintained diff --git a/rust/meson.build b/rust/meson.build index e69de29bb2..4a58d106b1 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -0,0 +1 @@ +subdir('qemu-api') diff --git a/rust/qemu-api/.gitignore b/rust/qemu-api/.gitignore new file mode 100644 index 0000000000..b9e7e004c8 --- /dev/null +++ b/rust/qemu-api/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs diff --git a/rust/qemu-api/Cargo.lock b/rust/qemu-api/Cargo.lock new file mode 100644 index 0000000000..e9c51a243a --- /dev/null +++ b/rust/qemu-api/Cargo.lock @@ -0,0 +1,7 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "qemu_api" +version =3D "0.1.0" diff --git a/rust/qemu-api/Cargo.toml b/rust/qemu-api/Cargo.toml new file mode 100644 index 0000000000..efc369e5ae --- /dev/null +++ b/rust/qemu-api/Cargo.toml @@ -0,0 +1,26 @@ +[package] +name =3D "qemu_api" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "Rust bindings for QEMU" +repository =3D "https://gitlab.com/qemu-project/qemu/" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[dependencies] + +[features] +default =3D ["allocator"] +allocator =3D [] + +# Do not include in any global workspace +[workspace] + +[lints.rust] +unexpected_cfgs =3D { level =3D "warn", check-cfg =3D ['cfg(MESON)', 'cfg(= HAVE_GLIB_WITH_ALIGNED_ALLOC)'] } diff --git a/rust/qemu-api/README.md b/rust/qemu-api/README.md new file mode 100644 index 0000000000..7588fa29ef --- /dev/null +++ b/rust/qemu-api/README.md @@ -0,0 +1,17 @@ +# QEMU bindings and API wrappers + +This library exports helper Rust types, Rust macros and C FFI bindings for= internal QEMU APIs. + +The C bindings can be generated with `bindgen`, using this build target: + +```console +$ ninja bindings.rs +``` + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items +``` diff --git a/rust/qemu-api/build.rs b/rust/qemu-api/build.rs new file mode 100644 index 0000000000..419b154c2d --- /dev/null +++ b/rust/qemu-api/build.rs @@ -0,0 +1,14 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use std::path::Path; + +fn main() { + if !Path::new("src/bindings.rs").exists() { + panic!( + "No generated C bindings found! Either build them manually wit= h bindgen or with meson \ + (`ninja bindings.rs`) and copy them to src/bindings.rs, or bu= ild through meson." + ); + } +} diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build new file mode 100644 index 0000000000..cf2b465e9f --- /dev/null +++ b/rust/qemu-api/meson.build @@ -0,0 +1,21 @@ +_qemu_api_rs =3D static_library( + 'qemu_api', + structured_sources( + [ + 'src/lib.rs', + 'src/definitions.rs', + 'src/device_class.rs', + ], + {'.' : bindings_rs}, + ), + override_options: ['rust_std=3D2021', 'build.rust_std=3D2021'], + rust_abi: 'rust', + rust_args: rustc_config_args + [ + '--cfg', 'MESON', + '--cfg', 'feature=3D"allocator"', + ], +) + +qemu_api =3D declare_dependency( + link_with: _qemu_api_rs, +) diff --git a/rust/qemu-api/src/definitions.rs b/rust/qemu-api/src/definitio= ns.rs new file mode 100644 index 0000000000..4abd0253bd --- /dev/null +++ b/rust/qemu-api/src/definitions.rs @@ -0,0 +1,109 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Definitions required by QEMU when registering a device. + +/// Trait a type must implement to be registered with QEMU. +pub trait ObjectImpl { + type Class; + const TYPE_INFO: crate::bindings::TypeInfo; + const TYPE_NAME: &'static ::core::ffi::CStr; + const PARENT_TYPE_NAME: Option<&'static ::core::ffi::CStr>; + const INSTANCE_INIT: ::core::option::Option< + unsafe extern "C" fn(obj: *mut crate::bindings::Object), + >; + const INSTANCE_POST_INIT: ::core::option::Option< + unsafe extern "C" fn(obj: *mut crate::bindings::Object), + >; + const INSTANCE_FINALIZE: ::core::option::Option< + unsafe extern "C" fn(obj: *mut crate::bindings::Object), + >; + const ABSTRACT: bool; +} + +pub trait Class { + const CLASS_INIT: ::core::option::Option< + unsafe extern "C" fn( + klass: *mut crate::bindings::ObjectClass, + data: *mut core::ffi::c_void, + ), + >; + const CLASS_BASE_INIT: ::core::option::Option< + unsafe extern "C" fn( + klass: *mut crate::bindings::ObjectClass, + data: *mut core::ffi::c_void, + ), + >; +} + +#[macro_export] +macro_rules! module_init { + ($func:expr, $type:expr) =3D> { + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() =3D { + assert!($type < $crate::bindings::module_init_type_MODULE_INIT= _MAX); + + extern "C" fn __load() { + unsafe { + $crate::bindings::register_module_init(Some($func), $t= ype); + } + } + + __load + }; + }; + (qom: $func:ident =3D> $body:block) =3D> { + // NOTE: To have custom identifiers for the ctor func we need to e= ither supply + // them directly as a macro argument or create them with a proc ma= cro. + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() =3D { + extern "C" fn __load() { + #[no_mangle] + unsafe extern "C" fn $func() { + $body + } + + unsafe { + $crate::bindings::register_module_init( + Some($func), + $crate::bindings::module_init_type_MODULE_INIT_QOM, + ); + } + } + + __load + }; + }; +} + +#[macro_export] +macro_rules! type_info { + ($t:ty) =3D> { + $crate::bindings::TypeInfo { + name: <$t as $crate::definitions::ObjectImpl>::TYPE_NAME.as_pt= r(), + parent: if let Some(pname) =3D <$t as $crate::definitions::Obj= ectImpl>::PARENT_TYPE_NAME { + pname.as_ptr() + } else { + ::core::ptr::null_mut() + }, + instance_size: ::core::mem::size_of::<$t>(), + instance_align: ::core::mem::align_of::<$t>(), + instance_init: <$t as $crate::definitions::ObjectImpl>::INSTAN= CE_INIT, + instance_post_init: <$t as $crate::definitions::ObjectImpl>::I= NSTANCE_POST_INIT, + instance_finalize: <$t as $crate::definitions::ObjectImpl>::IN= STANCE_FINALIZE, + abstract_: <$t as $crate::definitions::ObjectImpl>::ABSTRACT, + class_size: ::core::mem::size_of::<<$t as $crate::definitions= ::ObjectImpl>::Class>(), + class_init: <<$t as $crate::definitions::ObjectImpl>::Class as= $crate::definitions::Class>::CLASS_INIT, + class_base_init: <<$t as $crate::definitions::ObjectImpl>::Cla= ss as $crate::definitions::Class>::CLASS_BASE_INIT, + class_data: ::core::ptr::null_mut(), + interfaces: ::core::ptr::null_mut(), + }; + } +} diff --git a/rust/qemu-api/src/device_class.rs b/rust/qemu-api/src/device_c= lass.rs new file mode 100644 index 0000000000..69ee912c33 --- /dev/null +++ b/rust/qemu-api/src/device_class.rs @@ -0,0 +1,128 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use std::sync::OnceLock; + +use crate::bindings::Property; + +#[macro_export] +macro_rules! device_class_init { + ($func:ident, props =3D> $props:ident, realize_fn =3D> $realize_fn:exp= r, reset_fn =3D> $reset_fn:expr, vmsd =3D> $vmsd:ident$(,)*) =3D> { + #[no_mangle] + pub unsafe extern "C" fn $func( + klass: *mut $crate::bindings::ObjectClass, + _: *mut ::core::ffi::c_void, + ) { + let mut dc =3D + ::core::ptr::NonNull::new(klass.cast::<$crate::bindings::D= eviceClass>()).unwrap(); + dc.as_mut().realize =3D $realize_fn; + dc.as_mut().reset =3D $reset_fn; + dc.as_mut().vmsd =3D &$vmsd; + $crate::bindings::device_class_set_props(dc.as_mut(), $props.a= s_mut_ptr()); + } + }; +} + +#[macro_export] +macro_rules! define_property { + ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr, default = =3D $defval:expr$(,)*) =3D> { + $crate::bindings::Property { + name: { + #[used] + static _TEMP: &::core::ffi::CStr =3D $name; + _TEMP.as_ptr() + }, + info: $prop, + offset: ::core::mem::offset_of!($state, $field) + .try_into() + .expect("Could not fit offset value to type"), + bitnr: 0, + bitmask: 0, + set_default: true, + defval: $crate::bindings::Property__bindgen_ty_1 { u: $defval.= into() }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; + ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr$(,)*) =3D>= { + $crate::bindings::Property { + name: { + #[used] + static _TEMP: &::core::ffi::CStr =3D $name; + _TEMP.as_ptr() + }, + info: $prop, + offset: ::core::mem::offset_of!($state, $field) + .try_into() + .expect("Could not fit offset value to type"), + bitnr: 0, + bitmask: 0, + set_default: false, + defval: $crate::bindings::Property__bindgen_ty_1 { i: 0 }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; +} + +#[repr(C)] +pub struct Properties(pub OnceLock<[Property; N]>, pub fn(= ) -> [Property; N]); + +impl Properties { + pub fn as_mut_ptr(&mut self) -> *mut Property { + _ =3D self.0.get_or_init(self.1); + self.0.get_mut().unwrap().as_mut_ptr() + } +} + +#[macro_export] +macro_rules! declare_properties { + ($ident:ident, $($prop:expr),*$(,)*) =3D> { + + const fn _calc_prop_len() -> usize { + let mut len =3D 1; + $({ + _ =3D stringify!($prop); + len +=3D 1; + })* + len + } + const PROP_LEN: usize =3D _calc_prop_len(); + + fn _make_properties() -> [$crate::bindings::Property; PROP_LEN] { + [ + $($prop),*, + unsafe { ::core::mem::MaybeUninit::<$crate::bindings::= Property>::zeroed().assume_init() }, + ] + } + + #[no_mangle] + pub static mut $ident: $crate::device_class::Properties = =3D $crate::device_class::Properties(::std::sync::OnceLock::new(), _make_pr= operties); + }; +} + +#[macro_export] +macro_rules! vm_state_description { + ($(#[$outer:meta])* + $name:ident, + $(name: $vname:expr,)* + $(unmigratable: $um_val:expr,)* + ) =3D> { + #[used] + $(#[$outer])* + pub static $name: $crate::bindings::VMStateDescription =3D $crate:= :bindings::VMStateDescription { + $(name: { + #[used] + static VMSTATE_NAME: &::core::ffi::CStr =3D $vname; + $vname.as_ptr() + },)* + unmigratable: true, + ..unsafe { ::core::mem::MaybeUninit::<$crate::bindings::VMStat= eDescription>::zeroed().assume_init() } + }; + } +} diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs new file mode 100644 index 0000000000..2663702490 --- /dev/null +++ b/rust/qemu-api/src/lib.rs @@ -0,0 +1,154 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +#![cfg_attr(not(MESON), doc =3D include_str!("../README.md"))] + +#[allow( + dead_code, + improper_ctypes_definitions, + improper_ctypes, + non_camel_case_types, + non_snake_case, + non_upper_case_globals, + clippy::missing_const_for_fn, + clippy::too_many_arguments, + clippy::approx_constant, + clippy::use_self, + clippy::useless_transmute, + clippy::missing_safety_doc, +)] +#[rustfmt::skip] +pub mod bindings; + +unsafe impl Send for bindings::Property {} +unsafe impl Sync for bindings::Property {} +unsafe impl Sync for bindings::TypeInfo {} +unsafe impl Sync for bindings::VMStateDescription {} + +pub mod definitions; +pub mod device_class; + +#[cfg(test)] +mod tests; + +use std::alloc::{GlobalAlloc, Layout}; + +#[cfg(HAVE_GLIB_WITH_ALIGNED_ALLOC)] +extern "C" { + fn g_aligned_alloc0( + n_blocks: bindings::gsize, + n_block_bytes: bindings::gsize, + alignment: bindings::gsize, + ) -> bindings::gpointer; + fn g_aligned_free(mem: bindings::gpointer); +} + +#[cfg(not(HAVE_GLIB_WITH_ALIGNED_ALLOC))] +extern "C" { + fn qemu_memalign(alignment: usize, size: usize) -> *mut ::core::ffi::c= _void; + fn qemu_vfree(ptr: *mut ::core::ffi::c_void); +} + +extern "C" { + fn g_malloc0(n_bytes: bindings::gsize) -> bindings::gpointer; + fn g_free(mem: bindings::gpointer); +} + +/// An allocator that uses the same allocator as QEMU in C. +/// +/// It is enabled by default with the `allocator` feature. +/// +/// To set it up manually as a global allocator in your crate: +/// +/// ```ignore +/// use qemu_api::QemuAllocator; +/// +/// #[global_allocator] +/// static GLOBAL: QemuAllocator =3D QemuAllocator::new(); +/// ``` +#[derive(Clone, Copy, Debug)] +#[repr(C)] +pub struct QemuAllocator { + _unused: [u8; 0], +} + +#[cfg_attr(all(feature =3D "allocator", not(test)), global_allocator)] +pub static GLOBAL: QemuAllocator =3D QemuAllocator::new(); + +impl QemuAllocator { + // From the glibc documentation, on GNU systems, malloc guarantees 16-= byte + // alignment on 64-bit systems and 8-byte alignment on 32-bit systems.= See + // https://www.gnu.org/software/libc/manual/html_node/Malloc-Examples.= html. + // This alignment guarantee also applies to Windows and Android. On Da= rwin + // and OpenBSD, the alignment is 16 bytes on both 64-bit and 32-bit sy= stems. + #[cfg(all( + target_pointer_width =3D "32", + not(any(target_os =3D "macos", target_os =3D "openbsd")) + ))] + pub const DEFAULT_ALIGNMENT_BYTES: Option =3D Some(8); + #[cfg(all( + target_pointer_width =3D "64", + not(any(target_os =3D "macos", target_os =3D "openbsd")) + ))] + pub const DEFAULT_ALIGNMENT_BYTES: Option =3D Some(16); + #[cfg(all( + any(target_pointer_width =3D "32", target_pointer_width =3D "64"), + any(target_os =3D "macos", target_os =3D "openbsd") + ))] + pub const DEFAULT_ALIGNMENT_BYTES: Option =3D Some(16); + #[cfg(not(any(target_pointer_width =3D "32", target_pointer_width =3D = "64")))] + pub const DEFAULT_ALIGNMENT_BYTES: Option =3D None; + + pub const fn new() -> Self { + Self { _unused: [] } + } +} + +impl Default for QemuAllocator { + fn default() -> Self { + Self::new() + } +} + +// Sanity check. +const _: [(); 8] =3D [(); ::core::mem::size_of::<*mut ::core::ffi::c_void>= ()]; + +unsafe impl GlobalAlloc for QemuAllocator { + unsafe fn alloc(&self, layout: Layout) -> *mut u8 { + if matches!(Self::DEFAULT_ALIGNMENT_BYTES, Some(default) if defaul= t.checked_rem(layout.align()) =3D=3D Some(0)) + { + g_malloc0(layout.size().try_into().unwrap()).cast::() + } else { + #[cfg(HAVE_GLIB_WITH_ALIGNED_ALLOC)] + { + g_aligned_alloc0( + layout.size().try_into().unwrap(), + 1, + (8 * layout.align()).try_into().unwrap(), + ) + .cast::() + } + #[cfg(not(HAVE_GLIB_WITH_ALIGNED_ALLOC))] + { + qemu_memalign(8 * layout.align(), layout.size()).cast::() + } + } + } + + unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { + if matches!(Self::DEFAULT_ALIGNMENT_BYTES, Some(default) if defaul= t.checked_rem(layout.align()) =3D=3D Some(0)) + { + g_free(ptr.cast::<_>()) + } else { + #[cfg(HAVE_GLIB_WITH_ALIGNED_ALLOC)] + { + g_aligned_free(ptr.cast::<_>()) + } + #[cfg(not(HAVE_GLIB_WITH_ALIGNED_ALLOC))] + { + qemu_vfree(ptr.cast::<_>()) + } + } + } +} diff --git a/rust/qemu-api/src/tests.rs b/rust/qemu-api/src/tests.rs new file mode 100644 index 0000000000..df54edbd4e --- /dev/null +++ b/rust/qemu-api/src/tests.rs @@ -0,0 +1,49 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use crate::{ + bindings::*, declare_properties, define_property, device_class_init, v= m_state_description, +}; + +#[test] +fn test_device_decl_macros() { + // Test that macros can compile. + vm_state_description! { + VMSTATE, + name: c"name", + unmigratable: true, + } + + #[repr(C)] + pub struct DummyState { + pub char_backend: CharBackend, + pub migrate_clock: bool, + } + + declare_properties! { + DUMMY_PROPERTIES, + define_property!( + c"chardev", + DummyState, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + define_property!( + c"migrate-clk", + DummyState, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), + } + + device_class_init! { + dummy_class_init, + props =3D> DUMMY_PROPERTIES, + realize_fn =3D> None, + reset_fn =3D> None, + vmsd =3D> VMSTATE, + } +} diff --git a/rust/rustfmt.toml b/rust/rustfmt.toml new file mode 100644 index 0000000000..ebecb99fe0 --- /dev/null +++ b/rust/rustfmt.toml @@ -0,0 +1,7 @@ +edition =3D "2021" +format_generated_files =3D false +format_code_in_doc_comments =3D true +format_strings =3D true +imports_granularity =3D "Crate" +group_imports =3D "StdExternalCrate" +wrap_comments =3D true --=20 2.45.2 From nobody Sun Nov 24 07:49:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1724757901; cv=none; d=zohomail.com; s=zohoarc; b=U/lV5Yy4hsUFFQk4udxbfxeRHKaEmgqYgHWI/L5oXT5xY8K/nW1XEv0XbOamKVsjsWUVbpQ47lksrgEKNXvCNEEMoVNayFWRkMWQjBWAK+hBrmaYwxfoEteCxG5Tdu56H3wXIWE2WGFHEfl93TPneiCjkLa2uvU9pNR/tX8vIRY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724757901; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=i3+mtYYzHBBtikw1zXv7DKh3kbgt/BPOlVSFhrrwD3U=; b=PvLQzWElUEB0d4wFysUlUdFZA6Yu2lZIru1dOZ5OnGFb+LiUr2I8TQBczuS3qF8DbwnA2qpy9inqXZ1ySgk9ZS40kw7U7VpKaJGasFDI6X7njaPqZaMBaB8+3MD7mJoBGb8z4mxf7SMb5RTBffixyRvIUTzKrwudY1diYp7CVUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1724757901638881.8754373898723; Tue, 27 Aug 2024 04:25:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1siuIt-0003Dv-Nk; Tue, 27 Aug 2024 07:24:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1siuIr-00035z-OI for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:24:01 -0400 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1siuIp-0000m8-Ht for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:24:01 -0400 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-5334b0e1a8eso7050819e87.0 for ; Tue, 27 Aug 2024 04:23:59 -0700 (PDT) Received: from [127.0.1.1] (adsl-242.37.6.163.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757901920116600 This commit adds a helper crate library, qemu-api-macros for derive (and other procedural) macros to be used along qemu-api. It needs to be a separate library because in Rust, procedural macros, or macros that can generate arbitrary code, need to be special separate compilation units. Only one macro is introduced in this patch, #[derive(Object)]. It generates a constructor to register a QOM TypeInfo on init and it must be used on types that implement qemu_api::definitions::ObjectImpl trait. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 1 + rust/meson.build | 1 + rust/qemu-api-macros/Cargo.lock | 47 ++++++++++++++++++++++++++++++++++++= ++++ rust/qemu-api-macros/Cargo.toml | 25 +++++++++++++++++++++ rust/qemu-api-macros/README.md | 1 + rust/qemu-api-macros/meson.build | 25 +++++++++++++++++++++ rust/qemu-api-macros/src/lib.rs | 43 ++++++++++++++++++++++++++++++++++++ rust/qemu-api/meson.build | 3 +++ 8 files changed, 146 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d35e9f6b20..727f3a7a2c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3352,6 +3352,7 @@ Rust M: Manos Pitsidianakis S: Maintained F: rust/qemu-api +F: rust/qemu-api-macros F: rust/rustfmt.toml =20 SLIRP diff --git a/rust/meson.build b/rust/meson.build index 4a58d106b1..7a32b1b195 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -1 +1,2 @@ +subdir('qemu-api-macros') subdir('qemu-api') diff --git a/rust/qemu-api-macros/Cargo.lock b/rust/qemu-api-macros/Cargo.l= ock new file mode 100644 index 0000000000..fdc0fce116 --- /dev/null +++ b/rust/qemu-api-macros/Cargo.lock @@ -0,0 +1,47 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "proc-macro2" +version =3D "1.0.86" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "5e719e8df665df0d1c8fbfd238015744736151d4445ec0836b8e628aae10= 3b77" +dependencies =3D [ + "unicode-ident", +] + +[[package]] +name =3D "qemu_api_macros" +version =3D "0.1.0" +dependencies =3D [ + "proc-macro2", + "quote", + "syn", +] + +[[package]] +name =3D "quote" +version =3D "1.0.36" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208ac= aca7" +dependencies =3D [ + "proc-macro2", +] + +[[package]] +name =3D "syn" +version =3D "2.0.72" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "dc4b9b9bf2add8093d3f2c0204471e951b2285580335de42f9d2534f3ae7= a8af" +dependencies =3D [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name =3D "unicode-ident" +version =3D "1.0.12" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" diff --git a/rust/qemu-api-macros/Cargo.toml b/rust/qemu-api-macros/Cargo.t= oml new file mode 100644 index 0000000000..144cc3650f --- /dev/null +++ b/rust/qemu-api-macros/Cargo.toml @@ -0,0 +1,25 @@ +[package] +name =3D "qemu_api_macros" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "Rust bindings for QEMU - Utility macros" +repository =3D "https://gitlab.com/qemu-project/qemu/" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[lib] +proc-macro =3D true + +[dependencies] +proc-macro2 =3D "1" +quote =3D "1" +syn =3D "2" + +# Do not include in any global workspace +[workspace] diff --git a/rust/qemu-api-macros/README.md b/rust/qemu-api-macros/README.md new file mode 100644 index 0000000000..f60f54ac4b --- /dev/null +++ b/rust/qemu-api-macros/README.md @@ -0,0 +1 @@ +# `qemu-api-macros` - Utility macros for defining QEMU devices diff --git a/rust/qemu-api-macros/meson.build b/rust/qemu-api-macros/meson.= build new file mode 100644 index 0000000000..48af91ed38 --- /dev/null +++ b/rust/qemu-api-macros/meson.build @@ -0,0 +1,25 @@ +add_languages('rust', required: true, native: true) + +quote_dep =3D dependency('quote-1-rs', native: true) +syn_dep =3D dependency('syn-2-rs', native: true) +proc_macro2_dep =3D dependency('proc-macro2-1-rs', native: true) + +_qemu_api_macros_rs =3D import('rust').proc_macro( + 'qemu_api_macros', + files('src/lib.rs'), + override_options: ['rust_std=3D2021', 'build.rust_std=3D2021'], + rust_args: [ + '--cfg', 'use_fallback', + '--cfg', 'feature=3D"syn-error"', + '--cfg', 'feature=3D"proc-macro"', + ], + dependencies: [ + proc_macro2_dep, + quote_dep, + syn_dep, + ], +) + +qemu_api_macros =3D declare_dependency( + link_with: _qemu_api_macros_rs, +) diff --git a/rust/qemu-api-macros/src/lib.rs b/rust/qemu-api-macros/src/lib= .rs new file mode 100644 index 0000000000..331bc9e215 --- /dev/null +++ b/rust/qemu-api-macros/src/lib.rs @@ -0,0 +1,43 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use proc_macro::TokenStream; +use quote::{format_ident, quote}; +use syn::{parse_macro_input, DeriveInput}; + +#[proc_macro_derive(Object)] +pub fn derive_object(input: TokenStream) -> TokenStream { + let input =3D parse_macro_input!(input as DeriveInput); + + let name =3D input.ident; + let module_static =3D format_ident!("__{}_LOAD_MODULE", name); + + let expanded =3D quote! { + #[allow(non_upper_case_globals)] + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static #module_static: extern "C" fn() =3D { + extern "C" fn __register() { + unsafe { + ::qemu_api::bindings::type_register_static(&<#name as = ::qemu_api::definitions::ObjectImpl>::TYPE_INFO); + } + } + + extern "C" fn __load() { + unsafe { + ::qemu_api::bindings::register_module_init( + Some(__register), + ::qemu_api::bindings::module_init_type_MODULE_INIT= _QOM + ); + } + } + + __load + }; + }; + + TokenStream::from(expanded) +} diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build index cf2b465e9f..2030c24ed9 100644 --- a/rust/qemu-api/meson.build +++ b/rust/qemu-api/meson.build @@ -14,6 +14,9 @@ _qemu_api_rs =3D static_library( '--cfg', 'MESON', '--cfg', 'feature=3D"allocator"', ], + dependencies: [ + qemu_api_macros, + ], ) =20 qemu_api =3D declare_dependency( --=20 2.45.2 From nobody Sun Nov 24 07:49:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1724757910; cv=none; d=zohomail.com; s=zohoarc; b=kJwzOj986wAzFtSnQCfl6tO1xNwUY0WN8B2A2vyXDWT2/tBEdAKpWL8XOiTpCrL5c8i0XaQHhJK3f5JsZHVtjOzH4DOghCkdxc2dSF7ya0RuNN1MwJPb7D7tBWh/uNstKVaoukoCrVrMchR5ID1diXzyzqnavqoJ89vPpXD8aCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1724757910; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b5mnfcu34BODDUbbppuIPt4g7BhWrzd0FVXNvbQvg9Y=; b=CHLO7bqR7PzguTO/tij4/AyO7MEFNGhO8YCMeyzMD/hpAkSQMNx6uSsqNPFH65yZs0MW1hjmjAqxvj74tW00ofMgvdtiOEFrlsjRjwEesAoQ6o5V89ea4+9J7dzRDZAGoczjueDiQc82bF+OdqPAJQfF0248iqOpp7qbp8x7Wes= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172475791091832.250285626647496; Tue, 27 Aug 2024 04:25:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1siuJ1-0003hZ-10; Tue, 27 Aug 2024 07:24:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1siuIz-0003ab-9P for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:24:09 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1siuIt-0000mz-Dl for qemu-devel@nongnu.org; Tue, 27 Aug 2024 07:24:08 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a83597ce5beso832521266b.1 for ; Tue, 27 Aug 2024 04:24:01 -0700 (PDT) Received: from [127.0.1.1] (adsl-242.37.6.163.tellas.gr. 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a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724757912207116600 This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=3Daarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device Co-authored-by: Junjie Mao Co-authored-by: Paolo Bonzini Signed-off-by: Junjie Mao Signed-off-by: Paolo Bonzini Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 + meson.build | 24 + hw/arm/Kconfig | 33 +- rust/Kconfig | 1 + rust/hw/Kconfig | 2 + rust/hw/char/Kconfig | 3 + rust/hw/char/meson.build | 1 + rust/hw/char/pl011/.gitignore | 2 + rust/hw/char/pl011/Cargo.lock | 134 +++++ rust/hw/char/pl011/Cargo.toml | 26 + rust/hw/char/pl011/README.md | 31 ++ rust/hw/char/pl011/meson.build | 26 + rust/hw/char/pl011/src/definitions.rs | 20 + rust/hw/char/pl011/src/device.rs | 594 +++++++++++++++++= ++++ rust/hw/char/pl011/src/device_class.rs | 59 ++ rust/hw/char/pl011/src/lib.rs | 585 +++++++++++++++++= +++ rust/hw/char/pl011/src/memory_ops.rs | 57 ++ rust/hw/meson.build | 1 + rust/meson.build | 2 + scripts/archive-source.sh | 5 +- scripts/make-release | 5 +- scripts/rust/rust_root_crate.sh | 13 + subprojects/.gitignore | 11 + subprojects/arbitrary-int-1-rs.wrap | 7 + subprojects/bilge-0.2-rs.wrap | 7 + subprojects/bilge-impl-0.2-rs.wrap | 7 + subprojects/either-1-rs.wrap | 7 + subprojects/itertools-0.11-rs.wrap | 7 + .../packagefiles/arbitrary-int-1-rs/meson.build | 19 + subprojects/packagefiles/bilge-0.2-rs/meson.build | 29 + .../packagefiles/bilge-impl-0.2-rs/meson.build | 45 ++ subprojects/packagefiles/either-1-rs/meson.build | 24 + .../packagefiles/itertools-0.11-rs/meson.build | 30 ++ .../packagefiles/proc-macro-error-1-rs/meson.build | 40 ++ .../proc-macro-error-attr-1-rs/meson.build | 32 ++ .../packagefiles/proc-macro2-1-rs/meson.build | 31 ++ subprojects/packagefiles/quote-1-rs/meson.build | 29 + subprojects/packagefiles/syn-2-rs/meson.build | 40 ++ .../packagefiles/unicode-ident-1-rs/meson.build | 20 + subprojects/proc-macro-error-1-rs.wrap | 7 + subprojects/proc-macro-error-attr-1-rs.wrap | 7 + subprojects/proc-macro2-1-rs.wrap | 7 + subprojects/quote-1-rs.wrap | 7 + subprojects/syn-2-rs.wrap | 7 + subprojects/unicode-ident-1-rs.wrap | 7 + 45 files changed, 2043 insertions(+), 13 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 727f3a7a2c..cb65018b4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1189,6 +1189,11 @@ F: include/hw/*/microbit*.h F: tests/qtest/microbit-test.c F: docs/system/arm/nrf.rst =20 +ARM PL011 Rust device +M: Manos Pitsidianakis +S: Maintained +F: rust/hw/char/pl011/ + AVR Machines ------------- =20 diff --git a/meson.build b/meson.build index 7f05466d12..a4249fc24f 100644 --- a/meson.build +++ b/meson.build @@ -3489,6 +3489,7 @@ qom_ss =3D ss.source_set() system_ss =3D ss.source_set() specific_fuzz_ss =3D ss.source_set() specific_ss =3D ss.source_set() +rust_devices_ss =3D ss.source_set() stub_ss =3D ss.source_set() trace_ss =3D ss.source_set() user_ss =3D ss.source_set() @@ -4002,6 +4003,29 @@ foreach target : target_dirs arch_srcs +=3D target_specific.sources() arch_deps +=3D target_specific.dependencies() =20 + if have_rust and have_system + target_rust =3D rust_devices_ss.apply(config_target, strict: false) + crates =3D [] + foreach dep : target_rust.dependencies() + crates +=3D dep.get_variable('crate') + endforeach + if crates.length() > 0 + rlib_rs =3D custom_target('rust_' + target.underscorify() + '.rs', + output: 'rust_' + target.underscorify() + '.= rs', + command: [find_program('scripts/rust/rust_ro= ot_crate.sh')] + crates, + capture: true, + build_by_default: true, + build_always_stale: true) + rlib =3D static_library('rust_' + target.underscorify(), + rlib_rs, + dependencies: target_rust.dependencies(), + override_options: ['rust_std=3D2021', 'build.r= ust_std=3D2021'], + rust_args: rustc_config_args, + rust_abi: 'c') + arch_deps +=3D declare_dependency(link_whole: [rlib]) + endif + endif + # allow using headers from the dependencies but do not include the sourc= es, # because this emulator only needs those in "objects". For external # dependencies, the full dependency is included below in the executable. diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 1ad60da7aa..45438c1bc4 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -20,7 +20,8 @@ config ARM_VIRT select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL061 # GPIO select GPIO_PWR @@ -80,7 +81,8 @@ config HIGHBANK select AHCI select ARM_TIMER # sp804 select ARM_V7M - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL022 # SPI select PL031 # RTC select PL061 # GPIO @@ -93,7 +95,8 @@ config INTEGRATOR depends on TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL041 # audio select PL050 # keyboard/mouse @@ -119,7 +122,8 @@ config MUSCA default y depends on TCG && ARM select ARMSSE - select PL011 + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 select SPLIT_IRQ select UNIMP @@ -228,7 +232,8 @@ config Z2 depends on TCG && ARM select PFLASH_CFI01 select WM8750 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PXA2XX =20 config REALVIEW @@ -248,7 +253,8 @@ config REALVIEW select WM8750 # audio codec select LSI_SCSI_PCI select PCI - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL041 # audio codec select PL050 # keyboard/mouse @@ -273,7 +279,8 @@ config SBSA_REF select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL061 # GPIO select USB_XHCI_SYSBUS @@ -297,7 +304,8 @@ config STELLARIS select ARM_V7M select CMSDK_APB_WATCHDOG select I2C - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL022 # SPI select PL061 # GPIO select SSD0303 # OLED display @@ -356,7 +364,8 @@ config VEXPRESS select ARM_TIMER # sp804 select LAN9118 select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL041 # audio codec select PL181 # display select REALVIEW @@ -440,7 +449,8 @@ config RASPI default y depends on TCG && ARM select FRAMEBUFFER - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select SDHCI select USB_DWC2 select BCM2835_SPI @@ -515,7 +525,8 @@ config XLNX_VERSAL select ARM_GIC select CPU_CLUSTER select DEVICE_TREE - select PL011 + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select CADENCE select VIRTIO_MMIO select UNIMP diff --git a/rust/Kconfig b/rust/Kconfig index e69de29bb2..f9f5c39098 100644 --- a/rust/Kconfig +++ b/rust/Kconfig @@ -0,0 +1 @@ +source hw/Kconfig diff --git a/rust/hw/Kconfig b/rust/hw/Kconfig new file mode 100644 index 0000000000..4d934f30af --- /dev/null +++ b/rust/hw/Kconfig @@ -0,0 +1,2 @@ +# devices Kconfig +source char/Kconfig diff --git a/rust/hw/char/Kconfig b/rust/hw/char/Kconfig new file mode 100644 index 0000000000..a1732a9e97 --- /dev/null +++ b/rust/hw/char/Kconfig @@ -0,0 +1,3 @@ +config X_PL011_RUST + bool + default y if HAVE_RUST diff --git a/rust/hw/char/meson.build b/rust/hw/char/meson.build new file mode 100644 index 0000000000..5716dc43ef --- /dev/null +++ b/rust/hw/char/meson.build @@ -0,0 +1 @@ +subdir('pl011') diff --git a/rust/hw/char/pl011/.gitignore b/rust/hw/char/pl011/.gitignore new file mode 100644 index 0000000000..71eaff2035 --- /dev/null +++ b/rust/hw/char/pl011/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/hw/char/pl011/Cargo.lock b/rust/hw/char/pl011/Cargo.lock new file mode 100644 index 0000000000..b58cebb186 --- /dev/null +++ b/rust/hw/char/pl011/Cargo.lock @@ -0,0 +1,134 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "arbitrary-int" +version =3D "1.2.7" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b1d= f46d" + +[[package]] +name =3D "bilge" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512e6= 7b57" +dependencies =3D [ + "arbitrary-int", + "bilge-impl", +] + +[[package]] +name =3D "bilge-impl" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "feb11e002038ad243af39c2068c8a72bcf147acf05025dcdb916fcc000ad= b2d8" +dependencies =3D [ + "itertools", + "proc-macro-error", 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"registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cd= cff5" +dependencies =3D [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name =3D "unicode-ident" +version =3D "1.0.12" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" + +[[package]] +name =3D "version_check" +version =3D "0.9.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e= 483f" diff --git a/rust/hw/char/pl011/Cargo.toml b/rust/hw/char/pl011/Cargo.toml new file mode 100644 index 0000000000..b089e3dded --- /dev/null +++ b/rust/hw/char/pl011/Cargo.toml @@ -0,0 +1,26 @@ +[package] +name =3D "pl011" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "pl011 device model for QEMU" +repository =3D "https://gitlab.com/epilys/rust-for-qemu" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[lib] +crate-type =3D ["staticlib"] + +[dependencies] +bilge =3D { version =3D "0.2.0" } +bilge-impl =3D { version =3D "0.2.0" } +qemu_api =3D { path =3D "../../../qemu-api" } +qemu_api_macros =3D { path =3D "../../../qemu-api-macros" } + +# Do not include in any global workspace +[workspace] diff --git a/rust/hw/char/pl011/README.md b/rust/hw/char/pl011/README.md new file mode 100644 index 0000000000..cd7dea3163 --- /dev/null +++ b/rust/hw/char/pl011/README.md @@ -0,0 +1,31 @@ +# PL011 QEMU Device Model + +This library implements a device model for the PrimeCell=C2=AE UART (PL011) +device in QEMU. + +## Build static lib + +Host build target must be explicitly specified: + +```sh +cargo build --target x86_64-unknown-linux-gnu +``` + +Replace host target triplet if necessary. + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items --target x86_64-unknown-linux= -gnu +``` + +To include direct dependencies like `bilge` (bitmaps for register types): + +```sh +cargo tree --depth 1 -e normal --prefix none \ + | cut -d' ' -f1 \ + | xargs printf -- '-p %s\n' \ + | xargs cargo doc --no-deps --document-private-items --target x86_64-unkn= own-linux-gnu +``` diff --git a/rust/hw/char/pl011/meson.build b/rust/hw/char/pl011/meson.build new file mode 100644 index 0000000000..547cca5a96 --- /dev/null +++ b/rust/hw/char/pl011/meson.build @@ -0,0 +1,26 @@ +subproject('bilge-0.2-rs', required: true) +subproject('bilge-impl-0.2-rs', required: true) + +bilge_dep =3D dependency('bilge-0.2-rs') +bilge_impl_dep =3D dependency('bilge-impl-0.2-rs') + +_libpl011_rs =3D static_library( + 'pl011', + files('src/lib.rs'), + override_options: ['rust_std=3D2021', 'build.rust_std=3D2021'], + rust_abi: 'rust', + dependencies: [ + bilge_dep, + bilge_impl_dep, + qemu_api, + qemu_api_macros, + ], +) + +rust_devices_ss.add(when: 'CONFIG_X_PL011_RUST', if_true: [declare_depende= ncy( + link_whole: [_libpl011_rs], + # Putting proc macro crates in `dependencies` is necessary for Meson to = find + # them when compiling the root per-target static rust lib. + dependencies: [bilge_impl_dep, qemu_api_macros], + variables: {'crate': 'pl011'}, +)]) diff --git a/rust/hw/char/pl011/src/definitions.rs b/rust/hw/char/pl011/src= /definitions.rs new file mode 100644 index 0000000000..baafe1d390 --- /dev/null +++ b/rust/hw/char/pl011/src/definitions.rs @@ -0,0 +1,20 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Definitions required by QEMU when registering the device. + +use core::mem::MaybeUninit; + +use qemu_api::{bindings::*, definitions::ObjectImpl}; + +use crate::device::PL011State; + +pub const TYPE_PL011: &std::ffi::CStr =3D c"pl011"; + +#[used] +pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { + name: PL011State::TYPE_INFO.name, + unmigratable: true, + ..unsafe { MaybeUninit::::zeroed().assume_init() } +}; diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs new file mode 100644 index 0000000000..07cf2fa4e1 --- /dev/null +++ b/rust/hw/char/pl011/src/device.rs @@ -0,0 +1,594 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::{ + ffi::{c_int, c_uchar, c_uint, c_void, CStr}, + ptr::{addr_of, addr_of_mut, NonNull}, +}; + +use qemu_api::{ + bindings::{self, *}, + definitions::ObjectImpl, +}; + +use crate::{ + memory_ops::PL011_OPS, + registers::{self, Interrupt}, + RegisterOffset, +}; + +static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; + +const DATA_BREAK: u32 =3D 1 << 10; + +/// QEMU sourced constant. +pub const PL011_FIFO_DEPTH: usize =3D 16_usize; + +#[repr(C)] +#[derive(Debug, qemu_api_macros::Object)] +/// PL011 Device Model in QEMU +pub struct PL011State { + pub parent_obj: SysBusDevice, + pub iomem: MemoryRegion, + pub readbuff: u32, + #[doc(alias =3D "fr")] + pub flags: registers::Flags, + #[doc(alias =3D "lcr")] + pub line_control: registers::LineControl, + #[doc(alias =3D "rsr")] + pub receive_status_error_clear: registers::ReceiveStatusErrorClear, + #[doc(alias =3D "cr")] + pub control: registers::Control, + pub dmacr: u32, + pub int_enabled: u32, + pub int_level: u32, + pub read_fifo: [u32; PL011_FIFO_DEPTH], + pub ilpr: u32, + pub ibrd: u32, + pub fbrd: u32, + pub ifl: u32, + pub read_pos: usize, + pub read_count: usize, + pub read_trigger: usize, + #[doc(alias =3D "chr")] + pub char_backend: CharBackend, + /// QEMU interrupts + /// + /// ```text + /// * sysbus MMIO region 0: device registers + /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) + /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) + /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) + /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) + /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) + /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) + /// ``` + #[doc(alias =3D "irq")] + pub interrupts: [qemu_irq; 6usize], + #[doc(alias =3D "clk")] + pub clock: NonNull, + #[doc(alias =3D "migrate_clk")] + pub migrate_clock: bool, +} + +impl ObjectImpl for PL011State { + type Class =3D PL011Class; + const TYPE_INFO: qemu_api::bindings::TypeInfo =3D qemu_api::type_info!= { Self }; + const TYPE_NAME: &'static CStr =3D c"pl011"; + const PARENT_TYPE_NAME: Option<&'static CStr> =3D Some(TYPE_SYS_BUS_DE= VICE); + const ABSTRACT: bool =3D false; + const INSTANCE_INIT: Option = =3D Some(pl011_init); + const INSTANCE_POST_INIT: Option =3D None; + const INSTANCE_FINALIZE: Option =3D None; +} + +#[repr(C)] +pub struct PL011Class { + _inner: [u8; 0], +} + +impl qemu_api::definitions::Class for PL011Class { + const CLASS_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), + > =3D Some(crate::device_class::pl011_class_init); + const CLASS_BASE_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), + > =3D None; +} + +#[used] +pub static CLK_NAME: &CStr =3D c"clk"; + +impl PL011State { + pub fn init(&mut self) { + let dev =3D addr_of_mut!(*self).cast::(); + // SAFETY: + // + // self and self.iomem are guaranteed to be valid at this point si= nce callers + // must make sure the `self` reference is valid. + unsafe { + memory_region_init_io( + addr_of_mut!(self.iomem), + addr_of_mut!(*self).cast::(), + &PL011_OPS, + addr_of_mut!(*self).cast::(), + Self::TYPE_INFO.name, + 0x1000, + ); + let sbd =3D addr_of_mut!(*self).cast::(); + sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); + for irq in self.interrupts.iter_mut() { + sysbus_init_irq(sbd, irq); + } + } + // SAFETY: + // + // self.clock is not initialized at this point; but since `NonNull= <_>` is Copy, + // we can overwrite the undefined value without side effects. This= is + // safe since all PL011State instances are created by QOM code whi= ch + // calls this function to initialize the fields; therefore no code= is + // able to access an invalid self.clock value. + unsafe { + self.clock =3D NonNull::new(qdev_init_clock_in( + dev, + CLK_NAME.as_ptr(), + None, /* pl011_clock_update */ + addr_of_mut!(*self).cast::(), + ClockEvent_ClockUpdate, + )) + .unwrap(); + } + } + + pub fn read( + &mut self, + offset: hwaddr, + _size: core::ffi::c_uint, + ) -> std::ops::ControlFlow { + use RegisterOffset::*; + + std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset= ) { + Err(v) if (0x3f8..0x400).contains(&v) =3D> { + u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) + } + Err(_) =3D> { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + 0 + } + Ok(DR) =3D> { + // s->flags &=3D ~PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(false); + let c =3D self.read_fifo[self.read_pos]; + if self.read_count > 0 { + self.read_count -=3D 1; + self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); + } + if self.read_count =3D=3D 0 { + // self.flags |=3D PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(true); + } + if self.read_count + 1 =3D=3D self.read_trigger { + //self.int_level &=3D ~ INT_RX; + self.int_level &=3D !registers::INT_RX; + } + // Update error bits. + self.receive_status_error_clear =3D c.to_be_bytes()[3].int= o(); + self.update(); + // Must call qemu_chr_fe_accept_input, so return Continue: + return std::ops::ControlFlow::Continue(c.into()); + } + Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(), + Ok(FR) =3D> u16::from(self.flags).into(), + Ok(FBRD) =3D> self.fbrd.into(), + Ok(ILPR) =3D> self.ilpr.into(), + Ok(IBRD) =3D> self.ibrd.into(), + Ok(LCR_H) =3D> u16::from(self.line_control).into(), + Ok(CR) =3D> { + // We exercise our self-control. + u16::from(self.control).into() + } + Ok(FLS) =3D> self.ifl.into(), + Ok(IMSC) =3D> self.int_enabled.into(), + Ok(RIS) =3D> self.int_level.into(), + Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), + Ok(ICR) =3D> { + // "The UARTICR Register is the interrupt clear register a= nd is write-only" + // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR + 0 + } + Ok(DMACR) =3D> self.dmacr.into(), + }) + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + // eprintln!("write offset {offset} value {value}"); + use RegisterOffset::*; + let value: u32 =3D value as u32; + match RegisterOffset::try_from(offset) { + Err(_bad_offset) =3D> { + eprintln!("write bad offset {offset} value {value}"); + } + Ok(DR) =3D> { + // ??? Check if transmitter is enabled. + let ch: u8 =3D value as u8; + // XXX this blocks entire thread. Rewrite to use + // qemu_chr_fe_write and background I/O callbacks + + // SAFETY: self.char_backend is a valid CharBackend instan= ce after it's been + // initialized in realize(). + unsafe { + qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),= &ch, 1); + } + self.loopback_tx(value); + self.int_level |=3D registers::INT_TX; + self.update(); + } + Ok(RSR) =3D> { + self.receive_status_error_clear =3D 0.into(); + } + Ok(FR) =3D> { + // flag writes are ignored + } + Ok(ILPR) =3D> { + self.ilpr =3D value; + } + Ok(IBRD) =3D> { + self.ibrd =3D value; + } + Ok(FBRD) =3D> { + self.fbrd =3D value; + } + Ok(LCR_H) =3D> { + let value =3D value as u16; + let new_val: registers::LineControl =3D value.into(); + // Reset the FIFO state on FIFO enable or disable + if bool::from(self.line_control.fifos_enabled()) + ^ bool::from(new_val.fifos_enabled()) + { + self.reset_fifo(); + } + if self.line_control.send_break() ^ new_val.send_break() { + let mut break_enable: c_int =3D new_val.send_break().i= nto(); + // SAFETY: self.char_backend is a valid CharBackend in= stance after it's been + // initialized in realize(). + unsafe { + qemu_chr_fe_ioctl( + addr_of_mut!(self.char_backend), + CHR_IOCTL_SERIAL_SET_BREAK as i32, + addr_of_mut!(break_enable).cast::(), + ); + } + self.loopback_break(break_enable > 0); + } + self.line_control =3D new_val; + self.set_read_trigger(); + } + Ok(CR) =3D> { + // ??? Need to implement the enable bit. + let value =3D value as u16; + self.control =3D value.into(); + self.loopback_mdmctrl(); + } + Ok(FLS) =3D> { + self.ifl =3D value; + self.set_read_trigger(); + } + Ok(IMSC) =3D> { + self.int_enabled =3D value; + self.update(); + } + Ok(RIS) =3D> {} + Ok(MIS) =3D> {} + Ok(ICR) =3D> { + self.int_level &=3D !value; + self.update(); + } + Ok(DMACR) =3D> { + self.dmacr =3D value; + if value & 3 > 0 { + // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); + eprintln!("pl011: DMA not implemented"); + } + } + } + } + + #[inline] + fn loopback_tx(&mut self, value: u32) { + if !self.loopback_enabled() { + return; + } + + // Caveat: + // + // In real hardware, TX loopback happens at the serial-bit level + // and then reassembled by the RX logics back into bytes and placed + // into the RX fifo. That is, loopback happens after TX fifo. + // + // Because the real hardware TX fifo is time-drained at the frame + // rate governed by the configured serial format, some loopback + // bytes in TX fifo may still be able to get into the RX fifo + // that could be full at times while being drained at software + // pace. + // + // In such scenario, the RX draining pace is the major factor + // deciding which loopback bytes get into the RX fifo, unless + // hardware flow-control is enabled. + // + // For simplicity, the above described is not emulated. + self.put_fifo(value); + } + + fn loopback_mdmctrl(&mut self) { + if !self.loopback_enabled() { + return; + } + + /* + * Loopback software-driven modem control outputs to modem status = inputs: + * FR.RI <=3D CR.Out2 + * FR.DCD <=3D CR.Out1 + * FR.CTS <=3D CR.RTS + * FR.DSR <=3D CR.DTR + * + * The loopback happens immediately even if this call is triggered + * by setting only CR.LBE. + * + * CTS/RTS updates due to enabled hardware flow controls are not + * dealt with here. + */ + + //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | + // PL011_FLAG_DSR | PL011_FLAG_CTS); + //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; + //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; + //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; + //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; + // + self.flags.set_ring_indicator(self.control.out_2()); + self.flags.set_data_carrier_detect(self.control.out_1()); + self.flags.set_clear_to_send(self.control.request_to_send()); + self.flags + .set_data_set_ready(self.control.data_transmit_ready()); + + // Change interrupts based on updated FR + let mut il =3D self.int_level; + + il &=3D !Interrupt::MS; + //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; + //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; + //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; + //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; + + if self.flags.data_set_ready() { + il |=3D Interrupt::DSR as u32; + } + if self.flags.data_carrier_detect() { + il |=3D Interrupt::DCD as u32; + } + if self.flags.clear_to_send() { + il |=3D Interrupt::CTS as u32; + } + if self.flags.ring_indicator() { + il |=3D Interrupt::RI as u32; + } + self.int_level =3D il; + self.update(); + } + + fn loopback_break(&mut self, enable: bool) { + if enable { + self.loopback_tx(DATA_BREAK); + } + } + + fn set_read_trigger(&mut self) { + //#if 0 + // /* The docs say the RX interrupt is triggered when the FIFO = exceeds + // the threshold. However linux only reads the FIFO in resp= onse to an + // interrupt. Triggering the interrupt when the FIFO is non= -empty seems + // to make things work. */ + // if (s->lcr & LCR_FEN) + // s->read_trigger =3D (s->ifl >> 1) & 0x1c; + // else + //#endif + self.read_trigger =3D 1; + } + + pub fn realize(&mut self) { + // SAFETY: self.char_backend has the correct size and alignment fo= r a + // CharBackend object, and its callbacks are of the correct types. + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + pub fn reset(&mut self) { + self.line_control.reset(); + self.receive_status_error_clear.reset(); + self.dmacr =3D 0; + self.int_enabled =3D 0; + self.int_level =3D 0; + self.ilpr =3D 0; + self.ibrd =3D 0; + self.fbrd =3D 0; + self.read_trigger =3D 1; + self.ifl =3D 0x12; + self.control.reset(); + self.flags =3D 0.into(); + self.reset_fifo(); + } + + pub fn reset_fifo(&mut self) { + self.read_count =3D 0; + self.read_pos =3D 0; + + /* Reset FIFO flags */ + self.flags.reset(); + } + + pub fn can_receive(&self) -> bool { + // trace_pl011_can_receive(s->lcr, s->read_count, r); + self.read_count < self.fifo_depth() + } + + pub fn event(&mut self, event: QEMUChrEvent) { + if event =3D=3D bindings::QEMUChrEvent_CHR_EVENT_BREAK && !self.fi= fo_enabled() { + self.put_fifo(DATA_BREAK); + self.receive_status_error_clear.set_break_error(true); + } + } + + #[inline] + pub fn fifo_enabled(&self) -> bool { + matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) + } + + #[inline] + pub fn loopback_enabled(&self) -> bool { + self.control.enable_loopback() + } + + #[inline] + pub fn fifo_depth(&self) -> usize { + // Note: FIFO depth is expected to be power-of-2 + if self.fifo_enabled() { + return PL011_FIFO_DEPTH; + } + 1 + } + + pub fn put_fifo(&mut self, value: c_uint) { + let depth =3D self.fifo_depth(); + assert!(depth > 0); + let slot =3D (self.read_pos + self.read_count) & (depth - 1); + self.read_fifo[slot] =3D value; + self.read_count +=3D 1; + // s->flags &=3D ~PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(false); + if self.read_count =3D=3D depth { + //s->flags |=3D PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(true); + } + + if self.read_count =3D=3D self.read_trigger { + self.int_level |=3D registers::INT_RX; + self.update(); + } + } + + pub fn update(&mut self) { + let flags =3D self.int_level & self.int_enabled; + for (irq, i) in self.interrupts.iter().zip(IRQMASK) { + // SAFETY: self.interrupts have been initialized in init(). + unsafe { qemu_set_irq(*irq, i32::from(flags & i !=3D 0)) }; + } + } +} + +/// Which bits in the interrupt status matter for each outbound IRQ line ? +pub const IRQMASK: [u32; 6] =3D [ + /* combined IRQ */ + Interrupt::E + | Interrupt::MS + | Interrupt::RT as u32 + | Interrupt::TX as u32 + | Interrupt::RX as u32, + Interrupt::RX as u32, + Interrupt::TX as u32, + Interrupt::RT as u32, + Interrupt::MS, + Interrupt::E, +]; + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { + assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().can_receive().into() +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +/// +/// The buffer and size arguments must also be valid. +#[no_mangle] +pub unsafe extern "C" fn pl011_receive( + opaque: *mut core::ffi::c_void, + buf: *const u8, + size: core::ffi::c_int, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + if state.as_ref().loopback_enabled() { + return; + } + if size > 0 { + assert!(!buf.is_null()); + state + .as_mut() + .put_fifo(c_uint::from(unsafe { buf.read_volatile() })) + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().event(event) +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer for `c= hr`. +#[no_mangle] +pub unsafe extern "C" fn pl011_create( + addr: u64, + irq: qemu_irq, + chr: *mut Chardev, +) -> *mut DeviceState { + let dev: *mut DeviceState =3D unsafe { qdev_new(PL011State::TYPE_INFO.= name) }; + assert!(!dev.is_null()); + let sysbus: *mut SysBusDevice =3D dev as *mut SysBusDevice; + + qdev_prop_set_chr(dev, bindings::TYPE_CHARDEV.as_ptr(), chr); + sysbus_realize_and_unref(sysbus, addr_of!(error_fatal) as *mut *mut Er= ror); + sysbus_mmio_map(sysbus, 0, addr); + sysbus_connect_irq(sysbus, 0, irq); + dev +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_init(obj: *mut Object) { + assert!(!obj.is_null()); + let mut state =3D NonNull::new_unchecked(obj.cast::()); + state.as_mut().init(); +} diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr= c/device_class.rs new file mode 100644 index 0000000000..631d276e72 --- /dev/null +++ b/rust/hw/char/pl011/src/device_class.rs @@ -0,0 +1,59 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::ptr::NonNull; + +use qemu_api::bindings::*; + +use crate::{definitions::VMSTATE_PL011, device::PL011State}; + +qemu_api::declare_properties! { + PL011_PROPERTIES, + qemu_api::define_property!( + c"chardev", + PL011State, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + qemu_api::define_property!( + c"migrate-clk", + PL011State, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), +} + +qemu_api::device_class_init! { + pl011_class_init, + props =3D> PL011_PROPERTIES, + realize_fn =3D> Some(pl011_realize), + reset_fn =3D> Some(pl011_reset), + vmsd =3D> VMSTATE_PL011, +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().realize(); +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().reset(); +} diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs new file mode 100644 index 0000000000..54de89538a --- /dev/null +++ b/rust/hw/char/pl011/src/lib.rs @@ -0,0 +1,585 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later +// +// PL011 QEMU Device Model +// +// This library implements a device model for the PrimeCell=C2=AE UART (PL= 011) +// device in QEMU. +// +#![doc =3D include_str!("../README.md")] +//! # Library crate +//! +//! See [`PL011State`](crate::device::PL011State) for the device model typ= e and +//! the [`registers`] module for register types. + +#![deny( + rustdoc::broken_intra_doc_links, + rustdoc::redundant_explicit_links, + clippy::correctness, + clippy::suspicious, + clippy::complexity, + clippy::perf, + clippy::cargo, + clippy::nursery, + clippy::style, + // restriction group + clippy::dbg_macro, + clippy::as_underscore, + clippy::assertions_on_result_states, + // pedantic group + clippy::doc_markdown, + clippy::borrow_as_ptr, + clippy::cast_lossless, + clippy::option_if_let_else, + clippy::missing_const_for_fn, + clippy::cognitive_complexity, + clippy::missing_safety_doc, + )] + +extern crate bilge; +extern crate bilge_impl; +extern crate qemu_api; + +pub mod definitions; +pub mod device; +pub mod device_class; +pub mod memory_ops; + +/// Offset of each register from the base memory address of the device. +/// +/// # Source +/// ARM DDI 0183G, Table 3-1 p.3-3 +#[doc(alias =3D "offset")] +#[allow(non_camel_case_types)] +#[repr(u64)] +#[derive(Debug)] +pub enum RegisterOffset { + /// Data Register + /// + /// A write to this register initiates the actual data transmission + #[doc(alias =3D "UARTDR")] + DR =3D 0x000, + /// Receive Status Register or Error Clear Register + #[doc(alias =3D "UARTRSR")] + #[doc(alias =3D "UARTECR")] + RSR =3D 0x004, + /// Flag Register + /// + /// A read of this register shows if transmission is complete + #[doc(alias =3D "UARTFR")] + FR =3D 0x018, + /// Fractional Baud Rate Register + /// + /// responsible for baud rate speed + #[doc(alias =3D "UARTFBRD")] + FBRD =3D 0x028, + /// `IrDA` Low-Power Counter Register + #[doc(alias =3D "UARTILPR")] + ILPR =3D 0x020, + /// Integer Baud Rate Register + /// + /// Responsible for baud rate speed + #[doc(alias =3D "UARTIBRD")] + IBRD =3D 0x024, + /// line control register (data frame format) + #[doc(alias =3D "UARTLCR_H")] + LCR_H =3D 0x02C, + /// Toggle UART, transmission or reception + #[doc(alias =3D "UARTCR")] + CR =3D 0x030, + /// Interrupt FIFO Level Select Register + #[doc(alias =3D "UARTIFLS")] + FLS =3D 0x034, + /// Interrupt Mask Set/Clear Register + #[doc(alias =3D "UARTIMSC")] + IMSC =3D 0x038, + /// Raw Interrupt Status Register + #[doc(alias =3D "UARTRIS")] + RIS =3D 0x03C, + /// Masked Interrupt Status Register + #[doc(alias =3D "UARTMIS")] + MIS =3D 0x040, + /// Interrupt Clear Register + #[doc(alias =3D "UARTICR")] + ICR =3D 0x044, + /// DMA control Register + #[doc(alias =3D "UARTDMACR")] + DMACR =3D 0x048, + ///// Reserved, offsets `0x04C` to `0x07C`. + //Reserved =3D 0x04C, +} + +impl core::convert::TryFrom for RegisterOffset { + type Error =3D u64; + + fn try_from(value: u64) -> Result { + macro_rules! case { + ($($discriminant:ident),*$(,)*) =3D> { + /* check that matching on all macro arguments compiles, wh= ich means we are not + * missing any enum value; if the type definition ever cha= nges this will stop + * compiling. + */ + const fn _assert_exhaustive(val: RegisterOffset) { + match val { + $(RegisterOffset::$discriminant =3D> (),)* + } + } + + match value { + $(x if x =3D=3D Self::$discriminant as u64 =3D> Ok(Sel= f::$discriminant),)* + _ =3D> Err(value), + } + } + } + case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, = MIS, ICR, DMACR } + } +} + +pub mod registers { + //! Device registers exposed as typed structs which are backed by arbi= trary + //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. + //! + //! All PL011 registers are essentially 32-bit wide, but are typed her= e as + //! bitmaps with only the necessary width. That is, if a struct bitmap + //! in this module is for example 16 bits long, it should be conceived + //! as a 32-bit register where the unmentioned higher bits are always + //! unused thus treated as zero when read or written. + use bilge::prelude::*; + + // TODO: FIFO Mode has different semantics + /// Data Register, `UARTDR` + /// + /// The `UARTDR` register is the data register. + /// + /// For words to be transmitted: + /// + /// - if the FIFOs are enabled, data written to this location is pushe= d onto + /// the transmit + /// FIFO + /// - if the FIFOs are not enabled, data is stored in the transmitter + /// holding register (the + /// bottom word of the transmit FIFO). + /// + /// The write operation initiates transmission from the UART. The data= is + /// prefixed with a start bit, appended with the appropriate parity bit + /// (if parity is enabled), and a stop bit. The resultant word is then + /// transmitted. + /// + /// For received words: + /// + /// - if the FIFOs are enabled, the data byte and the 4-bit status (br= eak, + /// frame, parity, + /// and overrun) is pushed onto the 12-bit wide receive FIFO + /// - if the FIFOs are not enabled, the data byte and status are store= d in + /// the receiving + /// holding register (the bottom word of the receive FIFO). + /// + /// The received data byte is read by performing reads from the `UARTD= R` + /// register along with the corresponding status information. The stat= us + /// information can also be read by a read of the `UARTRSR/UARTECR` + /// register. + /// + /// # Note + /// + /// You must disable the UART before any of the control registers are + /// reprogrammed. When the UART is disabled in the middle of + /// transmission or reception, it completes the current character befo= re + /// stopping. + /// + /// # Source + /// ARM DDI 0183G 3.3.1 Data Register, UARTDR + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + #[doc(alias =3D "UARTDR")] + pub struct Data { + _reserved: u4, + pub data: u8, + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + } + + // TODO: FIFO Mode has different semantics + /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` + /// + /// The UARTRSR/UARTECR register is the receive status register/error = clear + /// register. Receive status can also be read from the `UARTRSR` + /// register. If the status is read from this register, then the status + /// information for break, framing and parity corresponds to the + /// data character read from the [Data register](Data), `UARTDR` prior= to + /// reading the UARTRSR register. The status information for overrun is + /// set immediately when an overrun condition occurs. + /// + /// + /// # Note + /// The received data character must be read first from the [Data + /// Register](Data), `UARTDR` before reading the error status associat= ed + /// with that data character from the `UARTRSR` register. This read + /// sequence cannot be reversed, because the `UARTRSR` register is + /// updated only when a read occurs from the `UARTDR` register. Howeve= r, + /// the status information can also be obtained by reading the `UARTDR` + /// register + /// + /// # Source + /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, + /// UARTRSR/UARTECR + #[bitsize(8)] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct ReceiveStatusErrorClear { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + + impl ReceiveStatusErrorClear { + pub fn reset(&mut self) { + // All the bits are cleared to 0 on reset. + *self =3D 0.into(); + } + } + + impl Default for ReceiveStatusErrorClear { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Flag Register, `UARTFR` + #[doc(alias =3D "UARTFR")] + pub struct Flags { + /// CTS Clear to send. This bit is the complement of the UART clea= r to + /// send, `nUARTCTS`, modem status input. That is, the bit is 1 + /// when `nUARTCTS` is LOW. + pub clear_to_send: bool, + /// DSR Data set ready. This bit is the complement of the UART dat= a set + /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 w= hen + /// `nUARTDSR` is LOW. + pub data_set_ready: bool, + /// DCD Data carrier detect. This bit is the complement of the UAR= T data + /// carrier detect, `nUARTDCD`, modem status input. That is, the b= it is + /// 1 when `nUARTDCD` is LOW. + pub data_carrier_detect: bool, + /// BUSY UART busy. If this bit is set to 1, the UART is busy + /// transmitting data. This bit remains set until the complete + /// byte, including all the stop bits, has been sent from the + /// shift register. This bit is set as soon as the transmit FIFO + /// becomes non-empty, regardless of whether the UART is enabled + /// or not. + pub busy: bool, + /// RXFE Receive FIFO empty. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the receive holding + /// register is empty. If the FIFO is enabled, the RXFE bit is + /// set when the receive FIFO is empty. + pub receive_fifo_empty: bool, + /// TXFF Transmit FIFO full. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the transmit holding + /// register is full. If the FIFO is enabled, the TXFF bit is + /// set when the transmit FIFO is full. + pub transmit_fifo_full: bool, + /// RXFF Receive FIFO full. The meaning of this bit depends on the= state + /// of the FEN bit in the UARTLCR_H register. If the FIFO is + /// disabled, this bit is set when the receive holding register + /// is full. If the FIFO is enabled, the RXFF bit is set when + /// the receive FIFO is full. + pub receive_fifo_full: bool, + /// Transmit FIFO empty. The meaning of this bit depends on the st= ate of + /// the FEN bit in the [Line Control register](LineControl), + /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the + /// transmit holding register is empty. If the FIFO is enabled, + /// the TXFE bit is set when the transmit FIFO is empty. This + /// bit does not indicate if there is data in the transmit shift + /// register. + pub transmit_fifo_empty: bool, + /// `RI`, is `true` when `nUARTRI` is `LOW`. + pub ring_indicator: bool, + _reserved_zero_no_modify: u7, + } + + impl Flags { + pub fn reset(&mut self) { + // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a= re 1 + self.set_receive_fifo_full(false); + self.set_transmit_fifo_full(false); + self.set_busy(false); + self.set_receive_fifo_empty(true); + self.set_transmit_fifo_empty(true); + } + } + + impl Default for Flags { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Line Control Register, `UARTLCR_H` + #[doc(alias =3D "UARTLCR_H")] + pub struct LineControl { + /// 15:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u8, + /// 7 SPS Stick parity select. + /// 0 =3D stick parity is disabled + /// 1 =3D either: + /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked + /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table= 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// b10 =3D 7 bits + /// b01 =3D 6 bits + /// b00 =3D 5 bits. + pub word_length: WordLength, + /// FEN Enable FIFOs: + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// EPS Even parity select. Controls the type of parity the UART u= ses + /// during transmission and reception: + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + /// This bit has no effect when the `PEN` bit disables parity chec= king + /// and generation. See Table 3-11 on page 3-14 for the parity + /// truth table. + pub parity: Parity, + /// 1 PEN Parity enable: + /// + /// - 0 =3D parity is disabled and no parity bit added to the data= frame + /// - 1 =3D parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output o= n the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break comma= nd, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + } + + impl LineControl { + pub fn reset(&mut self) { + // All the bits are cleared to 0 when reset. + *self =3D 0.into(); + } + } + + impl Default for LineControl { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `EPS` "Even parity select", field of [Line Control + /// register](LineControl). + pub enum Parity { + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + Odd =3D 0, + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + Even =3D 1, + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control + /// register](LineControl). + pub enum Mode { + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers + Character =3D 0, + /// 1 =3D transmit and receive FIFO buffers are enabled (FIFO mode= ). + FIFO =3D 1, + } + + impl From for bool { + fn from(val: Mode) -> Self { + matches!(val, Mode::FIFO) + } + } + + #[bitsize(2)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `WLEN` Word length, field of [Line Control register](LineControl). + /// + /// These bits indicate the number of data bits transmitted or receive= d in a + /// frame as follows: + pub enum WordLength { + /// b11 =3D 8 bits + _8Bits =3D 0b11, + /// b10 =3D 7 bits + _7Bits =3D 0b10, + /// b01 =3D 6 bits + _6Bits =3D 0b01, + /// b00 =3D 5 bits. + _5Bits =3D 0b00, + } + + /// Control Register, `UARTCR` + /// + /// The `UARTCR` register is the control register. All the bits are cl= eared + /// to `0` on reset except for bits `9` and `8` that are set to `1`. + /// + /// # Source + /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 + #[bitsize(16)] + #[doc(alias =3D "UARTCR")] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct Control { + /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is d= isabled + /// in the middle of transmission or reception, it completes the c= urrent + /// character before stopping. 1 =3D the UART is enabled. Data + /// transmission and reception occurs for either UART signals or S= IR + /// signals depending on the setting of the SIREN bit. + pub enable_uart: bool, + /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIRO= UT` + /// remains LOW (no light pulse generated), and signal transitions= on + /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is + /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains= HIGH, + /// in the marking state. Signal transitions on UARTRXD or modem s= tatus + /// inputs have no effect. This bit has no effect if the UARTEN bit + /// disables the UART. + pub enable_sir: bool, + /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA enc= oding + /// mode. If this bit is cleared to 0, low-level bits are transmit= ted as + /// an active high pulse with a width of 3/ 16th of the bit period= . If + /// this bit is set to 1, low-level bits are transmitted with a pu= lse + /// width that is 3 times the period of the IrLPBaud16 input signa= l, + /// regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + pub sir_lowpower_irda_mode: u1, + /// Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u4, + /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN b= it is + /// set to 1 and the SIRTEST bit in the Test Control register, UAR= TTCR + /// on page 4-5 is set to 1, then the nSIROUT path is inverted, an= d fed + /// through to the SIRIN path. The SIRTEST bit in the test registe= r must + /// be set to 1 to override the normal half-duplex SIR operation. = This + /// must be the requirement for accessing the test registers during + /// normal operation, and SIRTEST must be cleared to 0 when loopba= ck + /// testing is finished. This feature reduces the amount of extern= al + /// coupling required during system test. If this bit is set to 1,= and + /// the SIRTEST bit is set to 0, the UARTTXD path is fed through t= o the + /// UARTRXD path. In either SIR mode or UART mode, when this bit i= s set, + /// the modem outputs are also fed through to the modem inputs. Th= is bit + /// is cleared to 0 on reset, to disable loopback. + pub enable_loopback: bool, + /// `TXE` Transmit enable. If this bit is set to 1, the transmit s= ection + /// of the UART is enabled. Data transmission occurs for either UA= RT + /// signals, or SIR signals depending on the setting of the SIREN = bit. + /// When the UART is disabled in the middle of transmission, it + /// completes the current character before stopping. + pub enable_transmit: bool, + /// `RXE` Receive enable. If this bit is set to 1, the receive sec= tion + /// of the UART is enabled. Data reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN b= it. + /// When the UART is disabled in the middle of reception, it compl= etes + /// the current character before stopping. + pub enable_receive: bool, + /// `DTR` Data transmit ready. This bit is the complement of the U= ART + /// data transmit ready, `nUARTDTR`, modem status output. That is,= when + /// the bit is programmed to a 1 then `nUARTDTR` is LOW. + pub data_transmit_ready: bool, + /// `RTS` Request to send. This bit is the complement of the UART + /// request to send, `nUARTRTS`, modem status output. That is, whe= n the + /// bit is programmed to a 1 then `nUARTRTS` is LOW. + pub request_to_send: bool, + /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1= `) + /// modem status output. That is, when the bit is programmed to a = 1 the + /// output is 0. For DTE this can be used as Data Carrier Detect (= DCD). + pub out_1: bool, + /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2= `) + /// modem status output. That is, when the bit is programmed to a = 1, the + /// output is 0. For DTE this can be used as Ring Indicator (RI). + pub out_2: bool, + /// `RTSEn` RTS hardware flow control enable. If this bit is set t= o 1, + /// RTS hardware flow control is enabled. Data is only requested w= hen + /// there is space in the receive FIFO for it to be received. + pub rts_hardware_flow_control_enable: bool, + /// `CTSEn` CTS hardware flow control enable. If this bit is set t= o 1, + /// CTS hardware flow control is enabled. Data is only transmitted= when + /// the `nUARTCTS` signal is asserted. + pub cts_hardware_flow_control_enable: bool, + } + + impl Control { + pub fn reset(&mut self) { + *self =3D 0.into(); + self.set_enable_receive(true); + self.set_enable_transmit(true); + } + } + + impl Default for Control { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC + pub const INT_OE: u32 =3D 1 << 10; + pub const INT_BE: u32 =3D 1 << 9; + pub const INT_PE: u32 =3D 1 << 8; + pub const INT_FE: u32 =3D 1 << 7; + pub const INT_RT: u32 =3D 1 << 6; + pub const INT_TX: u32 =3D 1 << 5; + pub const INT_RX: u32 =3D 1 << 4; + pub const INT_DSR: u32 =3D 1 << 3; + pub const INT_DCD: u32 =3D 1 << 2; + pub const INT_CTS: u32 =3D 1 << 1; + pub const INT_RI: u32 =3D 1 << 0; + pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + + #[repr(u32)] + pub enum Interrupt { + OE =3D 1 << 10, + BE =3D 1 << 9, + PE =3D 1 << 8, + FE =3D 1 << 7, + RT =3D 1 << 6, + TX =3D 1 << 5, + RX =3D 1 << 4, + DSR =3D 1 << 3, + DCD =3D 1 << 2, + CTS =3D 1 << 1, + RI =3D 1 << 0, + } + + impl Interrupt { + pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + } +} + +// TODO: You must disable the UART before any of the control registers are +// reprogrammed. When the UART is disabled in the middle of transmission or +// reception, it completes the current character before stopping diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/= memory_ops.rs new file mode 100644 index 0000000000..a2552ba58e --- /dev/null +++ b/rust/hw/char/pl011/src/memory_ops.rs @@ -0,0 +1,57 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0-or-later + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::device::PL011State; + +pub static PL011_OPS: MemoryRegionOps =3D MemoryRegionOps { + read: Some(pl011_read), + write: Some(pl011_write), + read_with_attrs: None, + write_with_attrs: None, + endianness: device_endian_DEVICE_NATIVE_ENDIAN, + valid: unsafe { MaybeUninit::::zeroed()= .assume_init() }, + impl_: MemoryRegionOps__bindgen_ty_2 { + min_access_size: 4, + max_access_size: 4, + ..unsafe { MaybeUninit::::zeroed().= assume_init() } + }, +}; + +#[no_mangle] +unsafe extern "C" fn pl011_read( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + size: core::ffi::c_uint, +) -> u64 { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + let val =3D state.as_mut().read(addr, size); + match val { + std::ops::ControlFlow::Break(val) =3D> val, + std::ops::ControlFlow::Continue(val) =3D> { + // SAFETY: self.char_backend is a valid CharBackend instance a= fter it's been + // initialized in realize(). + let cb_ptr =3D core::ptr::addr_of_mut!(state.as_mut().char_bac= kend); + unsafe { qemu_chr_fe_accept_input(cb_ptr) }; + + val + } + } +} + +#[no_mangle] +unsafe extern "C" fn pl011_write( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + data: u64, + _size: core::ffi::c_uint, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().write(addr, data) +} diff --git a/rust/hw/meson.build b/rust/hw/meson.build new file mode 100644 index 0000000000..860196645e --- /dev/null +++ b/rust/hw/meson.build @@ -0,0 +1 @@ +subdir('char') diff --git a/rust/meson.build b/rust/meson.build index 7a32b1b195..def77389cd 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -1,2 +1,4 @@ subdir('qemu-api-macros') subdir('qemu-api') + +subdir('hw') diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh index 65af8063e4..8b06c16230 100755 --- a/scripts/archive-source.sh +++ b/scripts/archive-source.sh @@ -26,7 +26,10 @@ sub_file=3D"${sub_tdir}/submodule.tar" # independent of what the developer currently has initialized # in their checkout, because the build environment is completely # different to the host OS. -subprojects=3D"keycodemapdb libvfio-user berkeley-softfloat-3 berkeley-tes= tfloat-3" +subprojects=3D"keycodemapdb libvfio-user berkeley-softfloat-3 + berkeley-testfloat-3 arbitrary-int-1.2.7 bilge-0.2.0 bilge-impl-0.2.0 + either-1.12.0 itertools-0.11.0 proc-macro2-1.0.84 proc-macro-error-1.0.4 + proc-macro-error-attr-1.0.4 quote-1.0.36 syn-2.0.66 unicode-ident-1.0.12" sub_deinit=3D"" =20 function cleanup() { diff --git a/scripts/make-release b/scripts/make-release index 6e0433de24..841404274b 100755 --- a/scripts/make-release +++ b/scripts/make-release @@ -17,7 +17,10 @@ if [ $# -ne 2 ]; then fi =20 # Only include wraps that are invoked with subproject() -SUBPROJECTS=3D"libvfio-user keycodemapdb berkeley-softfloat-3 berkeley-tes= tfloat-3" +SUBPROJECTS=3D"libvfio-user keycodemapdb berkeley-softfloat-3 berkeley-tes= tfloat-3 + arbitrary-int-1.2.7 bilge-0.2.0 bilge-impl-0.2.0 either-1.12.0 itertools= -0.11.0 + proc-macro2-1.0.84 proc-macro-error-1.0.4 proc-macro-error-attr-1.0.4 + quote-1.0.36 syn-2.0.66 unicode-ident-1.0.12" =20 src=3D"$1" version=3D"$2" diff --git a/scripts/rust/rust_root_crate.sh b/scripts/rust/rust_root_crate= .sh new file mode 100755 index 0000000000..975bddf7f1 --- /dev/null +++ b/scripts/rust/rust_root_crate.sh @@ -0,0 +1,13 @@ +#!/bin/sh + +set -eu + +cat <