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Fri, 23 Aug 2024 21:57:04 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Mark Corbin , Ajeet Singh , Richard Henderson Subject: [PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying Date: Sat, 24 Aug 2024 14:56:24 +1000 Message-Id: <20240824045635.8978-7-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240824045635.8978-1-itachis@FreeBSD.org> References: <20240824045635.8978-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1724475547275116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 ++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv/target_arch_reg.h diff --git a/bsd-user/riscv/target_arch_reg.h b/bsd-user/riscv/target_arch_= reg.h new file mode 100644 index 0000000000..12b1c96b61 --- /dev/null +++ b/bsd-user/riscv/target_arch_reg.h @@ -0,0 +1,88 @@ +/* + * RISC-V register structures + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_REG_H +#define TARGET_ARCH_REG_H + +/* Compare with riscv/include/reg.h */ +typedef struct target_reg { + uint64_t ra; /* return address */ + uint64_t sp; /* stack pointer */ + uint64_t gp; /* global pointer */ + uint64_t tp; /* thread pointer */ + uint64_t t[7]; /* temporaries */ + uint64_t s[12]; /* saved registers */ + uint64_t a[8]; /* function arguments */ + uint64_t sepc; /* exception program counter */ + uint64_t sstatus; /* status register */ +} target_reg_t; + +typedef struct target_fpreg { + uint64_t fp_x[32][2]; /* Floating point registers */ + uint64_t fp_fcsr; /* Floating point control reg */ +} target_fpreg_t; + +#define tswapreg(ptr) tswapal(ptr) + +/* Compare with struct trapframe in riscv/include/frame.h */ +static inline void target_copy_regs(target_reg_t *regs, + const CPURISCVState *env) +{ + + regs->ra =3D tswapreg(env->gpr[1]); + regs->sp =3D tswapreg(env->gpr[2]); + regs->gp =3D tswapreg(env->gpr[3]); + regs->tp =3D tswapreg(env->gpr[4]); + + regs->t[0] =3D tswapreg(env->gpr[5]); + regs->t[1] =3D tswapreg(env->gpr[6]); + regs->t[2] =3D tswapreg(env->gpr[7]); + regs->t[3] =3D tswapreg(env->gpr[28]); + regs->t[4] =3D tswapreg(env->gpr[29]); + regs->t[5] =3D tswapreg(env->gpr[30]); + regs->t[6] =3D tswapreg(env->gpr[31]); + + regs->s[0] =3D tswapreg(env->gpr[8]); + regs->s[1] =3D tswapreg(env->gpr[9]); + regs->s[2] =3D tswapreg(env->gpr[18]); + regs->s[3] =3D tswapreg(env->gpr[19]); + regs->s[4] =3D tswapreg(env->gpr[20]); + regs->s[5] =3D tswapreg(env->gpr[21]); + regs->s[6] =3D tswapreg(env->gpr[22]); + regs->s[7] =3D tswapreg(env->gpr[23]); + regs->s[8] =3D tswapreg(env->gpr[24]); + regs->s[9] =3D tswapreg(env->gpr[25]); + regs->s[10] =3D tswapreg(env->gpr[26]); + regs->s[11] =3D tswapreg(env->gpr[27]); + + regs->a[0] =3D tswapreg(env->gpr[10]); + regs->a[1] =3D tswapreg(env->gpr[11]); + regs->a[2] =3D tswapreg(env->gpr[12]); + regs->a[3] =3D tswapreg(env->gpr[13]); + regs->a[4] =3D tswapreg(env->gpr[14]); + regs->a[5] =3D tswapreg(env->gpr[15]); + regs->a[6] =3D tswapreg(env->gpr[16]); + regs->a[7] =3D tswapreg(env->gpr[17]); + + regs->sepc =3D tswapreg(env->pc); +} + +#undef tswapreg + +#endif /* TARGET_ARCH_REG_H */ --=20 2.34.1