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Berrange" Cc: Ani Sinha , Richard Henderson , John Snow , qemu-ppc@nongnu.org, Fabiano Rosas Subject: [PATCH v4 22/35] tests/functional: Convert the riscv_opensbi avocado test into a standalone test Date: Wed, 21 Aug 2024 10:27:23 +0200 Message-ID: <20240821082748.65853-23-thuth@redhat.com> In-Reply-To: <20240821082748.65853-1-thuth@redhat.com> References: <20240821082748.65853-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 11 X-Spam_score: 1.1 X-Spam_bar: + X-Spam_report: (1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1724228986362116600 The avocado test defined test functions for both, riscv32 and riscv64. Since we can run the whole file with multiple targets in the new framework, we can now consolidate the functions so we have to only define one function per machine now. Reviewed-by: Alistair Francis Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Thomas Huth --- MAINTAINERS | 1 + tests/avocado/riscv_opensbi.py | 63 -------------------------- tests/functional/meson.build | 8 ++++ tests/functional/test_riscv_opensbi.py | 36 +++++++++++++++ 4 files changed, 45 insertions(+), 63 deletions(-) delete mode 100644 tests/avocado/riscv_opensbi.py create mode 100755 tests/functional/test_riscv_opensbi.py diff --git a/MAINTAINERS b/MAINTAINERS index 91f5a0545f..11cefa015e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,6 +337,7 @@ F: hw/intc/riscv* F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +F: tests/functional/test_riscv* F: tests/tcg/riscv64/ =20 RISC-V XThead* extensions diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py deleted file mode 100644 index bfff9cc3c3..0000000000 --- a/tests/avocado/riscv_opensbi.py +++ /dev/null @@ -1,63 +0,0 @@ -# OpenSBI boot test for RISC-V machines -# -# Copyright (c) 2022, Ventana Micro -# -# This work is licensed under the terms of the GNU GPL, version 2 or -# later. See the COPYING file in the top-level directory. - -from avocado_qemu import QemuSystemTest -from avocado_qemu import wait_for_console_pattern - -class RiscvOpenSBI(QemuSystemTest): - """ - :avocado: tags=3Daccel:tcg - """ - timeout =3D 5 - - def boot_opensbi(self): - self.vm.set_console() - self.vm.launch() - wait_for_console_pattern(self, 'Platform Name') - wait_for_console_pattern(self, 'Boot HART MEDELEG') - - def test_riscv32_spike(self): - """ - :avocado: tags=3Darch:riscv32 - :avocado: tags=3Dmachine:spike - """ - self.boot_opensbi() - - def test_riscv64_spike(self): - """ - :avocado: tags=3Darch:riscv64 - :avocado: tags=3Dmachine:spike - """ - self.boot_opensbi() - - def test_riscv32_sifive_u(self): - """ - :avocado: tags=3Darch:riscv32 - :avocado: tags=3Dmachine:sifive_u - """ - self.boot_opensbi() - - def test_riscv64_sifive_u(self): - """ - :avocado: tags=3Darch:riscv64 - :avocado: tags=3Dmachine:sifive_u - """ - self.boot_opensbi() - - def test_riscv32_virt(self): - """ - :avocado: tags=3Darch:riscv32 - :avocado: tags=3Dmachine:virt - """ - self.boot_opensbi() - - def test_riscv64_virt(self): - """ - :avocado: tags=3Darch:riscv64 - :avocado: tags=3Dmachine:virt - """ - self.boot_opensbi() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index d6a1a3a116..55021c4e4d 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -55,6 +55,14 @@ tests_ppc_thorough =3D [ 'ppc_bamboo', ] =20 +tests_riscv32_quick =3D [ + 'riscv_opensbi', +] + +tests_riscv64_quick =3D [ + 'riscv_opensbi', +] + tests_s390x_thorough =3D [ 's390x_ccw_virtio', 's390x_topology', diff --git a/tests/functional/test_riscv_opensbi.py b/tests/functional/test= _riscv_opensbi.py new file mode 100755 index 0000000000..d077e40f42 --- /dev/null +++ b/tests/functional/test_riscv_opensbi.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# +# OpenSBI boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from qemu_test import QemuSystemTest +from qemu_test import wait_for_console_pattern + +class RiscvOpenSBI(QemuSystemTest): + + timeout =3D 5 + + def boot_opensbi(self): + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv_spike(self): + self.set_machine('spike') + self.boot_opensbi() + + def test_riscv_sifive_u(self): + self.set_machine('sifive_u') + self.boot_opensbi() + + def test_riscv_virt(self): + self.set_machine('virt') + self.boot_opensbi() + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.46.0