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([203.56.140.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127af1888esm9210774b3a.149.2024.08.20.19.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 19:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1724207166; x=1724811966; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w37pH7YuBGYOWjqIybzdzbU05nLwB6boAQ2yePJtIGM=; b=FgPjS0elR7adqfmFvdyCELWKXa10VB0afTjv/lBhF0120+G/hspjcrfLh7YYxIQ5qz Pnqm/EOHFR4RCD/Wj7CeVnAqgelhVsXeUEL86U/5kFhuLaaXUuhkIrrJVwGRVoDXc58V NkD/E03gLcn72QqBpVpE4o4EV/sYOAsrQWOsbMAx8ZXvEqOMP3oNvpfay51hGsBPE7Pp AekjuQsGoBHl/3nA6K3oUCYkmETtP7XxWI++ZUmihxXVmC2QnTwsBF3LKCjE49lzYRP6 9d1xP5FH9c54k2xy3ZbVeL3V5yA4LWysHXNYaPzB0gEhMejzbfAFhvniGEQRzkxKGLQX VTvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724207166; x=1724811966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w37pH7YuBGYOWjqIybzdzbU05nLwB6boAQ2yePJtIGM=; b=AfLvile5NeGhPmNNyKk4mpVOaOssMfFUhjUWPnSilHIMJdir4mnegqLhIRWBtO+dZH HqyuAPrd4P2JgiZByiZB1FbBYFd6N5izj0Hm+eBpmFbiu88bzH2Z5YuAw9UkdKH3mg+Y k1UxWVQDWDNrExDsv28ronNxGZLit+InCKh7he3bt2HRu44RI4/Xu3KQuxApZDiCjYcM tj2sMm53TmWYsEHQncFwXm7a/0xBgINGsU45tgzGY8qdlOangxpykriL8+fPtnj9gPoE e9ZAC0MLoAyCYYBqfOw2+K+iWfM7PytSx4EwDsLLpt8TN2rJODGza8YWeHgUWUuPzEGB fuyw== X-Gm-Message-State: AOJu0YwOv8NO3YtURRVMh3E7n5hRuVfs6Y4AT9UATwpUw1qu7ULjM8ZY vMy3rcsZN2REX2cBKpEKNepo4uEVjRrbZhy9FE9jQYyYfGD0n0oASW1YAVocv2ZxGI2p5mX1eRd NXT4= X-Google-Smtp-Source: AGHT+IEWPdOVoSnv5hUqmi6fOvUVlTxyYQ/Zmo+uBXnjaaPFyDq4nVpatIbvBQLodFeL9Y+I+NUVHQ== X-Received: by 2002:a05:6870:169a:b0:270:4500:bdc2 with SMTP id 586e51a60fabf-2738be2e0f4mr966674fac.32.1724207165931; Tue, 20 Aug 2024 19:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , Pierrick Bouvier Subject: [PULL 5/5] target/i386: Fix tss access size in switch_tss_ra Date: Wed, 21 Aug 2024 12:25:48 +1000 Message-ID: <20240821022548.421745-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240821022548.421745-1-richard.henderson@linaro.org> References: <20240821022548.421745-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1724207217396116600 Content-Type: text/plain; charset="utf-8" The two limit_max variables represent size - 1, just like the encoding in the GDT, thus the 'old' access was off by one. Access the minimal size of the new tss: the complete tss contains the iopb, which may be a larger block than the access api expects, and irrelevant because the iopb is not accessed during the switch itself. Fixes: 8b131065080a ("target/i386/tcg: use X86Access for TSS access") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2511 Signed-off-by: Richard Henderson Message-Id: <20240819074052.207783-1-richard.henderson@linaro.org> Reviewed-by: Peter Maydell Reviewed-by: Pierrick Bouvier --- target/i386/tcg/seg_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index bab552cd53..3b8fd827e1 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -378,7 +378,7 @@ static int switch_tss_ra(CPUX86State *env, int tss_sele= ctor, =20 /* X86Access avoids memory exceptions during the task switch */ mmu_index =3D cpu_mmu_index_kernel(env); - access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max, + access_prepare_mmu(&old, env, env->tr.base, old_tss_limit_max + 1, MMU_DATA_STORE, mmu_index, retaddr); =20 if (source =3D=3D SWITCH_TSS_CALL) { @@ -386,7 +386,8 @@ static int switch_tss_ra(CPUX86State *env, int tss_sele= ctor, probe_access(env, tss_base, 2, MMU_DATA_STORE, mmu_index, retaddr); } - access_prepare_mmu(&new, env, tss_base, tss_limit, + /* While true tss_limit may be larger, we don't access the iopb here. = */ + access_prepare_mmu(&new, env, tss_base, tss_limit_max + 1, MMU_DATA_LOAD, mmu_index, retaddr); =20 /* save the current state in the old TSS */ --=20 2.43.0