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[121.45.122.195]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3ac7ca33dsm5988407a91.6.2024.08.16.10.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 10:10:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723828205; x=1724433005; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5JX4fMSWYAeIvZxxe4ZWzsUZ5Z4cADcMR98comH+Msg=; b=ZA+pnVRxRzvrVW/stIIWTdxRfj0wZbXxuFKxCnLkI3CjWmKJx9MVD/CxkIMXtQaPSB fXdvq6YhnxxHTiuS/C4ga/IW+WU3+2wBduyAJgdlRxh74T+R/zjWrSWcoaXws4w7sJ+w aRJ2YwSD76BOe13tSRbiy5DMQ6K9NioK3rqTNaFK3veaSdENXBDiqgnsM0+Hi4oNoUtK m38O+M3+yM2RMhKEjPTa5peUtKtsXnpFKfUwnGCIxeuaK5yiRVacl0GZeWqWQxW35mD3 hgbwNyhGw2Y/KvzBreZtxFQB2SCGTPIICCJhKJLXtljzTQ5zzfuQ8FFvWwl6DzBKnL+H LCUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723828205; x=1724433005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5JX4fMSWYAeIvZxxe4ZWzsUZ5Z4cADcMR98comH+Msg=; b=NOd2/W7+Zb6E0IY79VRn7gvF5S+FQ2KPY+t3kVocDPywpbnIgcsLlhCfjcj1WhOL7a GAGNeLDhsWutlSUv2MJhlBmChKrAcORwWN1zW2vi6NPkuVqsB1yt2QhkZwmK92gen6U/ LxC35yy741Yu39j4jbwgduRYm+uu5XLmaztLiwCvUswV0YfkWwucw6mtIsSgPqCruanL eGX88gWv06ky4vCOnWbuBr+wesksveA9NSoMjV96P4xrdEGkpDCs59EkBoDGKHOyytxK kdzD78sdytkjESgM/M968pWT/QnlQ7mpSlgMMDSymrMYEj+lY5ZvUc3eJE1CC8HQIH3d FmXQ== X-Gm-Message-State: AOJu0YypB1njSbl/RfTCJSoanxgHbp2kmKUaKOBnnsxpPKQQINQZL4Us JFzJjOCuohB9oK93CrKrSjojZ9XmlxRISBSxcNleV0jbMK5pPsBklyRQd1FsNVs= X-Google-Smtp-Source: AGHT+IEBzu9hMrO/SZuCyTgRZ+IjMCHP23Ulq8fmEaVfLwqUr1meFQhPEF5536nF8fnPglpHKXzELQ== X-Received: by 2002:a17:90a:8a02:b0:2d3:d0b7:da4 with SMTP id 98e67ed59e1d1-2d40569bc90mr129772a91.19.1723828205026; Fri, 16 Aug 2024 10:10:05 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Jessica Clarke , Kyle Evans , Richard Henderson Subject: [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Date: Sat, 17 Aug 2024 03:09:34 +1000 Message-Id: <20240816170949.238511-3-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240816170949.238511-1-itachis@FreeBSD.org> References: <20240816170949.238511-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=itachis6234@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1723828247656116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h index 28f56560e0..5b436b2ac9 100644 --- a/bsd-user/riscv/target_arch_cpu.h +++ b/bsd-user/riscv/target_arch_cpu.h @@ -36,4 +36,98 @@ static inline void target_cpu_init(CPURISCVState *env, env->pc =3D regs->sepc; } =20 +static inline void target_cpu_loop(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + int trapnr; + abi_long ret; + unsigned int syscall_num; + int32_t signo, code; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + signo =3D 0; + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + case RISCV_EXCP_U_ECALL: + syscall_num =3D env->gpr[xT0]; /* t0 */ + env->pc +=3D TARGET_INSN_SIZE; + /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */ + if (TARGET_FREEBSD_NR___syscall =3D=3D syscall_num || + TARGET_FREEBSD_NR_syscall =3D=3D syscall_num) { + ret =3D do_freebsd_syscall(env, + env->gpr[xA0], /* a0 */ + env->gpr[xA1], /* a1 */ + env->gpr[xA2], /* a2 */ + env->gpr[xA3], /* a3 */ + env->gpr[xA4], /* a4 */ + env->gpr[xA5], /* a5 */ + env->gpr[xA6], /* a6 */ + env->gpr[xA7], /* a7 */ + 0); + } else { + ret =3D do_freebsd_syscall(env, + syscall_num, + env->gpr[xA0], /* a0 */ + env->gpr[xA1], /* a1 */ + env->gpr[xA2], /* a2 */ + env->gpr[xA3], /* a3 */ + env->gpr[xA4], /* a4 */ + env->gpr[xA5], /* a5 */ + env->gpr[xA6], /* a6 */ + env->gpr[xA7] /* a7 */ + ); + } + + /* + * Compare to cpu_set_syscall_retval() in + * riscv/riscv/vm_machdep.c + */ + if (ret >=3D 0) { + env->gpr[xA0] =3D ret; /* a0 */ + env->gpr[xT0] =3D 0; /* t0 */ + } else if (ret =3D=3D -TARGET_ERESTART) { + env->pc -=3D TARGET_INSN_SIZE; + } else if (ret !=3D -TARGET_EJUSTRETURN) { + env->gpr[xA0] =3D -ret; /* a0 */ + env->gpr[xT0] =3D 1; /* t0 */ + } + break; + case RISCV_EXCP_ILLEGAL_INST: + signo =3D TARGET_SIGILL; + code =3D TARGET_ILL_ILLOPC; + break; + case RISCV_EXCP_BREAKPOINT: + signo =3D TARGET_SIGTRAP; + code =3D TARGET_TRAP_BRKPT; + break; + case EXCP_DEBUG: + signo =3D TARGET_SIGTRAP; + code =3D TARGET_TRAP_BRKPT; + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception " + "0x%x - aborting\n", trapnr); + cpu_dump_state(cs, stderr, 0); + abort(); + } + + if (signo) { + force_sig_fault(signo, code, env->pc); + } + + process_pending_signals(env); + } +} + #endif /* TARGET_ARCH_CPU_H */ --=20 2.34.1