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[121.45.122.195]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3ac7ca33dsm5988407a91.6.2024.08.16.10.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 10:10:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723828202; x=1724433002; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ym/1RGtoz5BJkkD8ymj93z+ybr4lmWN9RxIP/TytMpQ=; b=UeAkpH1yiI8/TSbLCQ3pEjkmb5xKMllXmDWRQrDxSGnSwt5Gzj9T9e0O8aMgg1HQNc KaaOdawCpCiUta+6cE9Dw+lKmlNZQrXK7xewASNChnMdLyu6C83Kg+oUstodjT60DsQz OmU7zrqvfKURPRv81kyyNoy5arRc1OYzDvr/zyuxi6BMI0IV13Qsm34bQHadlvVfUelt EKtp0YwTiOg6no+aQve2MsflaG7Y/S8b9Lm/be3FC5Al2GDXd+10yqB5NuFLiosj3btu 5BDHPLXqkNV0A2GDxGJpuaS7ToVV8Bic3n1WIITsR91RMCd64odvAkCVY2LCNV1natEi bGUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723828202; x=1724433002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ym/1RGtoz5BJkkD8ymj93z+ybr4lmWN9RxIP/TytMpQ=; b=Czgzm4eCucI0QU25/LGfiHfAoDLr4ZLfHIkH1DWpEi+byR6vA5Vexu5YDlDCv4Jo1e rKgKIrS5VjNN64F+l2yHdXI+IWmPzPYuF2+MwgnTKeW4dayg5e3xb8sygEdtUW2KM+S2 TgdouNN6fhX8Mwu0ce/Hc2yXnqf49jLHWSbDhP98J0xsYvn0vJdoUZfQ7NKBwI3lg9k1 fFZ7lGm80Ork48pECYGLB1teFuatbcogz5qOJuicV0qctUzRUemp9YednuYTF/YerCVk oqJEpUPcze7D0MzLQRC0/kgso8T4zr64XzXx2VUFDe41PRXy2KKzpRaY6lrB+owqKv0o Z8oQ== X-Gm-Message-State: AOJu0YySjiIg3o8yDZCzjI6bYHipzIfiJoawet5ZFkD92IpjCR24jjvk nc6H43itdLLeuYN3VwQuhC8YT6jCdQox+da3qWxSDRBYBoC7ISCufP3DBjvLVbU= X-Google-Smtp-Source: AGHT+IFPOSG5WmbWALNMXblVLepNJLE9RHUaLRJqUL5zDZEGt8TDp8xS0TtlYRZvjwVl17mF5FhC6w== X-Received: by 2002:a17:90b:897:b0:2d3:b83f:75a with SMTP id 98e67ed59e1d1-2d40569bda7mr130197a91.21.1723828202045; Fri, 16 Aug 2024 10:10:02 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Jessica Clarke Subject: [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Date: Sat, 17 Aug 2024 03:09:33 +1000 Message-Id: <20240816170949.238511-2-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240816170949.238511-1-itachis@FreeBSD.org> References: <20240816170949.238511-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=itachis6234@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1723828289903116600 Content-Type: text/plain; charset="utf-8" From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke --- bsd-user/riscv/target_arch_cpu.h | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 bsd-user/riscv/target_arch_cpu.h diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_= cpu.h new file mode 100644 index 0000000000..28f56560e0 --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.h @@ -0,0 +1,39 @@ +/* + * RISC-V CPU init and loop + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" + +#define TARGET_DEFAULT_CPU_MODEL "max" + +static inline void target_cpu_init(CPURISCVState *env, + struct target_pt_regs *regs) +{ + int i; + + for (i =3D 0; i < 32; i++) { + env->gpr[i] =3D regs->regs[i]; + } + + env->pc =3D regs->sepc; +} + +#endif /* TARGET_ARCH_CPU_H */ --=20 2.34.1