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Thu, 15 Aug 2024 18:07:37 -0700 (PDT) From: Deepak Gupta To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com, Deepak Gupta Subject: [PATCH v4 16/16] target/riscv: add trace-hooks for each case of sw-check exception Date: Thu, 15 Aug 2024 18:07:10 -0700 Message-ID: <20240816010711.3055425-17-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240816010711.3055425-1-debug@rivosinc.com> References: <20240816010711.3055425-1-debug@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=debug@rivosinc.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1723770635481116600 Content-Type: text/plain; charset="utf-8" Violations to control flow rules setup by zicfilp and zicfiss lead to software check exceptions. To debug and fix such sw check issues in guest , add trace-hooks for each case. Signed-off-by: Jim Shu Signed-off-by: Deepak Gupta --- target/riscv/helper.h | 3 +++ target/riscv/insn_trans/trans_rvi.c.inc | 3 +++ target/riscv/insn_trans/trans_rvzicfiss.c.inc | 1 + target/riscv/op_helper.c | 13 +++++++++++++ target/riscv/trace-events | 6 ++++++ target/riscv/translate.c | 2 ++ 6 files changed, 28 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e946ba61fd..6e90fbd225 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -123,6 +123,9 @@ DEF_HELPER_2(cbo_zero, void, env, tl) =20 /* helper to raise sw check exception */ DEF_HELPER_2(raise_sw_check_excep, void, env, tl) +/* helper functions to trace riscv cfi violations */ +DEF_HELPER_3(zicfilp_label_mismatch, void, env, tl, tl) +DEF_HELPER_3(zicfiss_ra_mismatch, void, env, tl, tl) =20 /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 936b430282..7021f8d3da 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -54,6 +54,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) /* * misaligned, according to spec we should raise sw check exce= ption */ + trace_zicfilp_unaligned_lpad_instr(ctx->base.pc_first); gen_helper_raise_sw_check_excep(tcg_env, tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL)); return true; @@ -66,6 +67,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) TCGv tmp =3D tcg_temp_new(); tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); + gen_helper_zicfilp_label_mismatch(tcg_env, tcg_constant_tl(a->labe= l), + tmp); gen_helper_raise_sw_check_excep(tcg_env, tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL)); gen_set_label(skip); diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index 67f5c7804a..f1cf7ca438 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -45,6 +45,7 @@ static bool gen_sspopchk(DisasContext *ctx, int rs1_reg) mxl_memop(ctx) | MO_ALIGN); TCGv rs1 =3D get_gpr(ctx, rs1_reg, EXT_NONE); tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); + gen_helper_zicfiss_ra_mismatch(tcg_env, data, rs1); gen_helper_raise_sw_check_excep(tcg_env, tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL)); gen_set_label(skip); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 9ec19c4afa..b681f0f1aa 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "trace.h" =20 /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, @@ -265,6 +266,18 @@ void helper_raise_sw_check_excep(CPURISCVState *env, t= arget_ulong swcheck_code) riscv_raise_exception(env, RISCV_EXCP_SW_CHECK, GETPC()); } =20 +void helper_zicfilp_label_mismatch(CPURISCVState *env, target_ulong lpad_l= abel, + target_ulong t2_label) +{ + trace_zicfilp_lpad_reg_mismatch(lpad_label, t2_label); +} + +void helper_zicfiss_ra_mismatch(CPURISCVState *env, target_ulong ssra, + target_ulong rs1) +{ + trace_zicfiss_sspopchk_reg_mismatch(ssra, rs1); +} + #ifndef CONFIG_USER_ONLY =20 target_ulong helper_sret(CPURISCVState *env) diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 49ec4d3b7d..9d5b61a2da 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -9,3 +9,9 @@ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, ui= nt64_t val) "hart %" =20 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read m= seccfg, val: 0x%" PRIx64 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write= mseccfg, val: 0x%" PRIx64 + +# zicfiss/lp +zicfiss_sspopchk_reg_mismatch(uint64_t ssra, uint64_t rs1) "shadow_stack_r= a: 0x%" PRIx64 ", rs1: 0x%" PRIx64 +zicfilp_missing_lpad_instr(uint64_t pc_first) "pc_first: 0x%" PRIx64 +zicfilp_unaligned_lpad_instr(uint64_t pc_next) "pc_next: 0x%" PRIx64 +zicfilp_lpad_reg_mismatch(uint64_t lpad_label, uint64_t t2_label) "lpad_la= bel: 0x%" PRIx64 ", t2_label: 0x%" PRIx64 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6fa98e88d9..fbef430848 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -35,6 +35,7 @@ #undef HELPER_H =20 #include "tcg/tcg-cpu.h" +#include "trace.h" =20 /* global register indices */ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; @@ -1348,6 +1349,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) */ tcg_set_insn_param(tcg_ctx->cfi_lp_check, 1, tcgv_i32_arg(tcg_constant_i32(1))); + trace_zicfilp_missing_lpad_instr(ctx->base.pc_first); } } =20 --=20 2.44.0