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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36e4cfee676sm10654792f8f.49.2024.08.13.08.20.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2024 08:20:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1723562459; x=1724167259; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9YuTGRjD2i97kf8nmOQNNKGq72EmNNRMMhomIVoZje0=; b=DZjI3yd0LTJm0K6+xVO1J+RCdtD6vM9uAVUB4LUpiMQ5TrePntQHn3D/KBbo84OQEU wZTtjE6ul5xvMPZNz1Dq/EjdZIMsuQhxGXrSqMIGYdpH7GT1Xcc9d3LDqQ51E5pl5S7m O7ExB2bURLIjV8Lqe5oXxWExgeKSzpu5Mn96ZhxXu+T+PbENd04SY2tub4JUd9URstH9 Y55gWM6FJh0h3fS2MCZFIyi5qioxD42YWaT+SMiZ5HMGhncCmIverpaXRYpwt03oMTeS TKZKMY7GmcxW2uNlTFv4453iYN2HLAxzcFqjf+EeFQLTYjJBPjYVQN2UMD/FRFMJw11I mRRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723562459; x=1724167259; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9YuTGRjD2i97kf8nmOQNNKGq72EmNNRMMhomIVoZje0=; b=nOitTTCURH1lahtxBmTfVKTjwC/8ZoBn4vaPa1IuZRbKO9PFwXR0nmwqhVPXh1GoNt z3uC8HX5+Mg0iFvXmNT3SmPch46M+kBX7Vw44garAN/Zx41Bi16lLEACJ9VAxYXIl9aN tA+sJRF2j6ybAyJ/g/mVSzl449nTU5sLR6/Ugzmhw/eSAzBNAt8+1uQyNobjTZXaDnIu Ck4GVRWFC0MLz8MQB/mY5oEjnUEQLvzCjrR6wPSvVfXCvZ+J7/eSTI1NuCchxWzZhsR8 g5Dg81lOvU0FilkumEwBafRtlSbKq0JlFLUf/zJBfXl/CmYr8++ULIUzosx9u3PaiAi+ Fm1g== X-Gm-Message-State: AOJu0YxYr0jDl+NSQoK85eYToSshhJ0Owd4xutpZX7/R8XsWHy8npcqh ZAHhC1TWH31WIpvoo2vh7enxPU5Xou1Jk9lfT9Be1BlpCTBZClchBxLpnhOKS8hLDq8T9jpTUL4 G X-Google-Smtp-Source: AGHT+IHrDgyFBoYtiVKdkenB3u/tzAfWxVSsi7oxeOYuR4saahY9pX62DJZv6sd2vN2XlAFDZzruFg== X-Received: by 2002:a05:6000:1083:b0:367:8a3b:2098 with SMTP id ffacd0b85a97d-3716ccd8312mr2058297f8f.3.1723562458708; Tue, 13 Aug 2024 08:20:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/4] target/arm: Update translation regime comment for new features Date: Tue, 13 Aug 2024 16:20:53 +0100 Message-Id: <20240813152054.2445099-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813152054.2445099-1-peter.maydell@linaro.org> References: <20240813152054.2445099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1723562533942116600 Content-Type: text/plain; charset="utf-8" We have a long comment describing the Arm architectural translation regimes and how we map them to QEMU MMU indexes. This comment has got a bit out of date: * FEAT_SEL2 allows Secure EL2 and corresponding new regimes * FEAT_RME introduces Realm state and its translation regimes * We now model the Cortex-R52 so that is no longer a hypothetical * We separated Secure Stage 2 and NonSecure Stage 2 MMU indexes * We have an MMU index per physical address spacea Add the missing pieces so that the list of architectural translation regimes matches the Arm ARM, and the list and count of QEMU MMU indexes in the comment matches the enum. Signed-off-by: Peter Maydell Tested-by: Bernhard Beschow Reviewed-by: Richard Henderson Message-id: 20240809160430.1144805-2-peter.maydell@linaro.org --- target/arm/cpu.h | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a12859fc533..216774f5d3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2772,8 +2772,14 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sy= nc); * + NonSecure EL1 & 0 stage 2 * + NonSecure EL2 * + NonSecure EL2 & 0 (ARMv8.1-VHE) - * + Secure EL1 & 0 - * + Secure EL3 + * + Secure EL1 & 0 stage 1 + * + Secure EL1 & 0 stage 2 (FEAT_SEL2) + * + Secure EL2 (FEAT_SEL2) + * + Secure EL2 & 0 (FEAT_SEL2) + * + Realm EL1 & 0 stage 1 (FEAT_RME) + * + Realm EL1 & 0 stage 2 (FEAT_RME) + * + Realm EL2 (FEAT_RME) + * + EL3 * If EL3 is 32-bit: * + NonSecure PL1 & 0 stage 1 * + NonSecure PL1 & 0 stage 2 @@ -2805,10 +2811,12 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. - * 7. we fold together the secure and non-secure regimes for A-profile, + * 7. we fold together most secure and non-secure regimes for A-profile, * because there are no banked system registers for aarch64, so the * process of switching between secure and non-secure is * already heavyweight. + * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, + * because both are in use simultaneously for Secure EL2. * * This gives us the following list of cases: * @@ -2820,14 +2828,15 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * EL2 EL2&0 +PAN * EL2 (aka NS PL2) * EL3 (aka S PL1) - * Physical (NS & S) - * Stage2 (NS & S) + * Stage2 Secure + * Stage2 NonSecure + * plus one TLB per Physical address space: S, NS, Realm, Root * - * for a total of 12 different mmu_idx. + * for a total of 14 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and - * EL2 if we ever model a Cortex-R52). + * EL2 for cores like the Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: --=20 2.34.1