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Tue, 13 Aug 2024 19:39:15 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549156; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=s41auOvuvSWYkWZrV+6/i6p4nZMm5ePpik2bsZvhZIE=; b=A2FWrD5M8rk7JxZCDxwAc0u1OYT6ySYZoF4DR4m5i/9rgDsWaMvK8z8MUo3EFrEOQSnhNUUZLn2tWF2qpwzMhqUbATgEzOVhZ/OgHJRPngrhi36XJktVXj6qnhlC7tQcAb4mXOZrBPUK+JZspnKFIGEHQ/Krqg2KhSBriyMLLeM= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes Date: Tue, 13 Aug 2024 19:34:29 +0800 Message-Id: <20240813113436.831-9-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d73a62b0f2..8a0de18257 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -23,3 +23,4 @@ C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) C_O1_I1(v, r) +C_O1_I2(v, v, v) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f60913e805..650b5eff1a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -289,6 +289,12 @@ typedef enum { OPC_VSE32_V =3D 0x6027 | V_SUMOP, OPC_VSE64_V =3D 0x7027 | V_SUMOP, =20 + OPC_VADD_VV =3D 0x57 | V_OPIVV, + OPC_VSUB_VV =3D 0x8000057 | V_OPIVV, + OPC_VAND_VV =3D 0x24000057 | V_OPIVV, + OPC_VOR_VV =3D 0x28000057 | V_OPIVV, + OPC_VXOR_VV =3D 0x2c000057 | V_OPIVV, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -2158,6 +2164,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_add_vec: + tcg_out_opc_vv(s, OPC_VADD_VV, a0, a1, a2, true); + break; + case INDEX_op_sub_vec: + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2, true); + break; + case INDEX_op_and_vec: + tcg_out_opc_vv(s, OPC_VAND_VV, a0, a1, a2, true); + break; + case INDEX_op_or_vec: + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a1, a2, true); + break; + case INDEX_op_xor_vec: + tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2177,6 +2198,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return 1; default: return 0; } @@ -2327,6 +2354,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return C_O1_I2(v, v, v); default: g_assert_not_reached(); } --=20 2.43.0