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Tue, 13 Aug 2024 19:38:44 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549124; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=EWLNDfrEi+dm1G2o4h4VZRsgZJgtPX8Bj5pEmlXuxw4=; b=GeOKLtjreW46i7NeGyBs4ZTXXm8REDmoOz4GXoVdc+fuk95OFcs4ecgft8AJ850prm87Y6Rm2n4bl3PDIC80OuBuXD0koOQrIGcLOr0u/BKrM2lpGmUreGGn40gHsH8I0Dce+OK52ZxjYflTpxVd4RvI52z5RBKEogqZKH6FoGk= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 07/15] tcg/riscv: Implement vector mov/dup{m/i} Date: Tue, 13 Aug 2024 19:34:28 +0800 Message-Id: <20240813113436.831-8-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f17d679d71..f60913e805 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -288,6 +288,10 @@ typedef enum { OPC_VSE16_V =3D 0x5027 | V_SUMOP, OPC_VSE32_V =3D 0x6027 | V_SUMOP, OPC_VSE64_V =3D 0x7027 | V_SUMOP, + + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, + OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, + OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, } RISCVInsn; =20 /* @@ -641,6 +645,13 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) case TCG_TYPE_I64: tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + tcg_debug_assert(ret > TCG_REG_V0 && arg > TCG_REG_V0); + tcg_target_set_vec_config(s, type, prev_vece); + tcg_out_opc_vv(s, OPC_VMV_V_V, ret, TCG_REG_V0, arg, true); + break; default: g_assert_not_reached(); } @@ -977,6 +988,33 @@ static void tcg_out_addsub2(TCGContext *s, } } =20 +static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned v= ece, + TCGReg dst, TCGReg src) +{ + tcg_target_set_vec_config(s, type, vece); + tcg_out_opc_vx(s, OPC_VMV_V_X, dst, TCG_REG_V0, src, true); + return true; +} + +static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned = vece, + TCGReg dst, TCGReg base, intptr_t offs= et) +{ + tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); + return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); +} + +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned = vece, + TCGReg dst, int64_t arg) +{ + if (arg < 16 && arg >=3D -16) { + tcg_target_set_vec_config(s, type, vece); + tcg_out_opc_vi(s, OPC_VMV_V_I, dst, TCG_REG_V0, arg, true); + return; + } + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); + tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); +} + static const struct { RISCVInsn op; bool swap; @@ -2111,6 +2149,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, tcg_target_set_vec_config(s, type, vece); } switch (opc) { + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_ld_vec: tcg_out_ld(s, type, a0, a1, a2); break; @@ -2282,6 +2323,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_st_vec: return C_O0_I2(v, r); + case INDEX_op_dup_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); default: --=20 2.43.0