From nobody Sun Nov 24 12:31:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723548990; cv=none; d=zohomail.com; s=zohoarc; b=CGJzzPJ3Ei51RNFP3GcqQdg1YDpGI25avJkGgioNjPIsc1RFm7GkS3hufAE8aVCJxeRrbaUw2hdbd++koPRBg6HDMb2Da8GLom+ldovqoEv5mLjoMlzFlpt7dPI5fmcEnGfGJYI8qxls2HJgdo/11RFFOZjy6WHxGROLxAgkmk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723548990; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/d1sDtis43VunngbSIzdip5vT8h3Xv64FIWtRrW2dj4=; b=K9ZLAvfq7tLnndzBqp0+3Rj5BRdReyxbsW52u5aBPr0rSKdHOkuCXNvmfnDwwhG7WEBPbns1JG+HlCcxPOSBtrUG9s2RKQr6JnFHzuKkHjWNkKnArJKy/8O+N+B6cWHu8b9z+rnruB/5riZnqHkOIyJ75HHSmQOKespjtEjWVw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1723548990290387.9694306134169; Tue, 13 Aug 2024 04:36:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sdpoY-0002kh-H5; Tue, 13 Aug 2024 07:35:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sdpoW-0002jf-GF; Tue, 13 Aug 2024 07:35:44 -0400 Received: from out30-98.freemail.mail.aliyun.com ([115.124.30.98]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sdpoU-0002UW-Et; Tue, 13 Aug 2024 07:35:44 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WCoya3q_1723548935) by smtp.aliyun-inc.com; Tue, 13 Aug 2024 19:35:36 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723548937; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/d1sDtis43VunngbSIzdip5vT8h3Xv64FIWtRrW2dj4=; b=adF6NbmFAd4RNUAsFGYPTUyORpZGuO6AwAVYouMz2H1eGmGv2j7mkTSEPrEuwU8ec5D7aIKilomObp3SF/CgEv57XfZcx5JLOhw9yWBaPHWxqM2FVmdGbKMG3ryX6UFbWC2m9znsxVEdXGiRyAKD72Wxap5C2GuGGG2j7+lhQxE= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 01/15] util: Add RISC-V vector extension probe in cpuinfo Date: Tue, 13 Aug 2024 19:34:22 +0800 Message-Id: <20240813113436.831-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.98; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-98.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1723548991055116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 1 + util/cpuinfo-riscv.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cp= uinfo.h index 2b00660e36..bf6ae51f72 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,6 +10,7 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 497ce12680..551821edef 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -33,7 +33,7 @@ static void sigill_handler(int signo, siginfo_t *si, void= *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO= _ZVE64X; unsigned info =3D cpuinfo; =20 if (info) { @@ -49,6 +49,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |=3D CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zve64x) + info |=3D CPUINFO_ZVE64X; #endif left &=3D ~info; =20 @@ -64,7 +67,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) && pair.key >=3D 0) { info |=3D pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |=3D pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; - left &=3D ~(CPUINFO_ZBA | CPUINFO_ZBB); + info |=3D pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : = 0; + left &=3D ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZVE64X); #ifdef RISCV_HWPROBE_EXT_ZICOND info |=3D pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICO= ND : 0; left &=3D ~CPUINFO_ZICOND; @@ -108,6 +112,18 @@ unsigned __attribute__((constructor)) cpuinfo_init(voi= d) left &=3D ~CPUINFO_ZICOND; } =20 + if (left & CPUINFO_ZVE64X) { + /* Probe for Vector: vsetivli t0,1,e64,m1,ta,ma */ + unsigned vl; + got_sigill =3D 0; + + asm volatile( + "vsetivli %0, 1, e64, m1, ta, ma\n\t" + : "=3Dr"(vl) : : "vl" + ); + info |=3D (got_sigill || vl !=3D 1) ? 0 : CPUINFO_ZVE64X; + } + sigaction(SIGILL, &sa_old, NULL); assert(left =3D=3D 0); } --=20 2.43.0