From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723548990; cv=none; d=zohomail.com; s=zohoarc; b=CGJzzPJ3Ei51RNFP3GcqQdg1YDpGI25avJkGgioNjPIsc1RFm7GkS3hufAE8aVCJxeRrbaUw2hdbd++koPRBg6HDMb2Da8GLom+ldovqoEv5mLjoMlzFlpt7dPI5fmcEnGfGJYI8qxls2HJgdo/11RFFOZjy6WHxGROLxAgkmk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723548990; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/d1sDtis43VunngbSIzdip5vT8h3Xv64FIWtRrW2dj4=; b=K9ZLAvfq7tLnndzBqp0+3Rj5BRdReyxbsW52u5aBPr0rSKdHOkuCXNvmfnDwwhG7WEBPbns1JG+HlCcxPOSBtrUG9s2RKQr6JnFHzuKkHjWNkKnArJKy/8O+N+B6cWHu8b9z+rnruB/5riZnqHkOIyJ75HHSmQOKespjtEjWVw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1723548990290387.9694306134169; Tue, 13 Aug 2024 04:36:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sdpoY-0002kh-H5; Tue, 13 Aug 2024 07:35:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sdpoW-0002jf-GF; Tue, 13 Aug 2024 07:35:44 -0400 Received: from out30-98.freemail.mail.aliyun.com ([115.124.30.98]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sdpoU-0002UW-Et; Tue, 13 Aug 2024 07:35:44 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WCoya3q_1723548935) by smtp.aliyun-inc.com; Tue, 13 Aug 2024 19:35:36 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723548937; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/d1sDtis43VunngbSIzdip5vT8h3Xv64FIWtRrW2dj4=; b=adF6NbmFAd4RNUAsFGYPTUyORpZGuO6AwAVYouMz2H1eGmGv2j7mkTSEPrEuwU8ec5D7aIKilomObp3SF/CgEv57XfZcx5JLOhw9yWBaPHWxqM2FVmdGbKMG3ryX6UFbWC2m9znsxVEdXGiRyAKD72Wxap5C2GuGGG2j7+lhQxE= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 01/15] util: Add RISC-V vector extension probe in cpuinfo Date: Tue, 13 Aug 2024 19:34:22 +0800 Message-Id: <20240813113436.831-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.98; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-98.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1723548991055116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- host/include/riscv/host/cpuinfo.h | 1 + util/cpuinfo-riscv.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cp= uinfo.h index 2b00660e36..bf6ae51f72 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -10,6 +10,7 @@ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) #define CPUINFO_ZICOND (1u << 3) +#define CPUINFO_ZVE64X (1u << 4) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 497ce12680..551821edef 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -33,7 +33,7 @@ static void sigill_handler(int signo, siginfo_t *si, void= *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned left =3D CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO= _ZVE64X; unsigned info =3D cpuinfo; =20 if (info) { @@ -49,6 +49,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |=3D CPUINFO_ZICOND; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zve64x) + info |=3D CPUINFO_ZVE64X; #endif left &=3D ~info; =20 @@ -64,7 +67,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) && pair.key >=3D 0) { info |=3D pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |=3D pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; - left &=3D ~(CPUINFO_ZBA | CPUINFO_ZBB); + info |=3D pair.value & RISCV_HWPROBE_IMA_V ? CPUINFO_ZVE64X : = 0; + left &=3D ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZVE64X); #ifdef RISCV_HWPROBE_EXT_ZICOND info |=3D pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICO= ND : 0; left &=3D ~CPUINFO_ZICOND; @@ -108,6 +112,18 @@ unsigned __attribute__((constructor)) cpuinfo_init(voi= d) left &=3D ~CPUINFO_ZICOND; } =20 + if (left & CPUINFO_ZVE64X) { + /* Probe for Vector: vsetivli t0,1,e64,m1,ta,ma */ + unsigned vl; + got_sigill =3D 0; + + asm volatile( + "vsetivli %0, 1, e64, m1, ta, ma\n\t" + : "=3Dr"(vl) : : "vl" + ); + info |=3D (got_sigill || vl !=3D 1) ? 0 : CPUINFO_ZVE64X; + } + sigaction(SIGILL, &sa_old, NULL); assert(left =3D=3D 0); } --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723548999; cv=none; d=zohomail.com; s=zohoarc; b=QyGyxH85d1m93BRuAPRjCG1EEEW3xtECR8EScNdFeVASIaiCGQQLpPIhuWdNcMlRhLku3PGM0s5lW6+Qz/nz5nduKJPEK6kI5KSdGi+ILcfUH7rDR11sm3fBhlqqa1SJPvovtBckXuvpAQ3vp51bbYKdwhTGKx8f9s3BMYw7SaY= ARC-Message-Signature: i=1; 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charset="utf-8" From: TANG Tiancheng The loop in the 32-bit case of the vector compare operation was incorrectly incrementing by 8 bytes per iteration instead of 4 bytes. This caused the function to process only half of the intended elements. Signed-off-by: TANG Tiancheng Fixes: 9622c697d1 (tcg: Add gvec compare with immediate and scalar operand) Reviewed-by: Liu Zhiwei --- tcg/tcg-op-gvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0308732d9b..78ee1ced80 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3939,7 +3939,7 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, u= int32_t dofs, uint32_t i; =20 tcg_gen_extrl_i64_i32(t1, c); - for (i =3D 0; i < oprsz; i +=3D 8) { + for (i =3D 0; i < oprsz; i +=3D 4) { tcg_gen_ld_i32(t0, tcg_env, aofs + i); tcg_gen_negsetcond_i32(cond, t0, t0, t1); tcg_gen_st_i32(t0, tcg_env, dofs + i); --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723548999; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=7AK5MBa+OFFOyBHmGkLLwGS+2t3aszxPpZggK7yCWgs=; b=LrRYmgrA5NFHmwbp8WXqe56zKaLgaa59cezDGAEvMS6GRIR/RaQ7HQBkcTR0jmQnYJfxyU6c6Z7yOLnpj2BK0j1BAxEl0VHeLao15/fDmJf93qXDrGijbBqmm9Yp8JA1Ja9+j6MiFs5DOMbFt/T+0kmlRzGdNmwlU8pMVmRCa1M= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 03/15] tcg: Fix register allocation constraints Date: Tue, 13 Aug 2024 19:34:24 +0800 Message-Id: <20240813113436.831-4-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng When allocating registers for input and output, ensure they match the available registers to avoid allocating illeagal registers. We should respect RISC-V vector extension's variable-length registers and LMUL-based register grouping. Coordinate with tcg_target_available_regs initialization tcg_target_init (behind this commit) to ensure proper handling of vector register constraints. Note: While mov_vec doesn't have constraints, dup_vec and other IRs do. We need to strengthen constraints for all IRs except mov_vec, and this is sufficient. Signed-off-by: TANG Tiancheng Fixes: 29f5e92502 (tcg: Introduce paired register allocation) Reviewed-by: Liu Zhiwei --- tcg/tcg.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 34e3056380..d26b42534d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4722,8 +4722,10 @@ static void tcg_reg_alloc_dup(TCGContext *s, const T= CGOp *op) return; } =20 - dup_out_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; - dup_in_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; + dup_out_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs & + tcg_target_available_regs[ots->type]; + dup_in_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs & + tcg_target_available_regs[its->type]; =20 /* Allocate the output register now. */ if (ots->val_type !=3D TEMP_VAL_REG) { @@ -4876,7 +4878,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) =20 reg =3D ts->reg; i_preferred_regs =3D 0; - i_required_regs =3D arg_ct->regs; + i_required_regs =3D arg_ct->regs & tcg_target_available_regs[ts->t= ype]; allocate_new_reg =3D false; copyto_new_reg =3D false; =20 @@ -5078,6 +5080,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) =20 /* satisfy the output constraints */ for(k =3D 0; k < nb_oargs; k++) { + TCGRegSet o_required_regs; i =3D def->args_ct[k].sort_index; arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; @@ -5085,17 +5088,19 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) =20 /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); + o_required_regs =3D arg_ct->regs & + tcg_target_available_regs[ts->type]; =20 switch (arg_ct->pair) { case 0: /* not paired */ if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { reg =3D new_args[arg_ct->alias_index]; } else if (arg_ct->newreg) { - reg =3D tcg_reg_alloc(s, arg_ct->regs, + reg =3D tcg_reg_alloc(s, o_required_regs, i_allocated_regs | o_allocated_reg= s, output_pref(op, k), ts->indirect_b= ase); } else { - reg =3D tcg_reg_alloc(s, arg_ct->regs, o_allocated_reg= s, + reg =3D tcg_reg_alloc(s, o_required_regs, o_allocated_= regs, output_pref(op, k), ts->indirect_b= ase); } break; @@ -5104,12 +5109,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) if (arg_ct->oalias) { reg =3D new_args[arg_ct->alias_index]; } else if (arg_ct->newreg) { - reg =3D tcg_reg_alloc_pair(s, arg_ct->regs, + reg =3D tcg_reg_alloc_pair(s, o_required_regs, i_allocated_regs | o_allocate= d_regs, output_pref(op, k), ts->indirect_base); } else { - reg =3D tcg_reg_alloc_pair(s, arg_ct->regs, o_allocate= d_regs, + reg =3D tcg_reg_alloc_pair(s, o_required_regs, + o_allocated_regs, output_pref(op, k), ts->indirect_base); } --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723549053; cv=none; d=zohomail.com; s=zohoarc; b=TbY6rTx5YPeYIBeQqM1d0LATwzetiL799bHPduWekPUt3oo8PpTTwbqOB6usnQQkE60TrqpYS9O1hWHMv0jZG+qaHbI9yxZZYL+twfLiy4dYpOgzG/rQv8vSIywurVVfmX9FDMGlxJ3U9ds3Ti1uA3Wb9nWorysy+A0ih2+g7A8= ARC-Message-Signature: i=1; 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charset="utf-8" From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. The unused register numbers within groups are implemented by adding constraints to tcg_target_available_regs during register allocation in tcg.c in the previous commit. This patch: 1. Reserves vector register 0 for use as a mask register. 2. When using register groups, reserves the additional registers within each group. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 151 ++++++++++++++++++++++++++------- tcg/riscv/tcg-target.h | 78 ++++++++++------- tcg/riscv/tcg-target.opc.h | 12 +++ 4 files changed, 177 insertions(+), 65 deletions(-) create mode 100644 tcg/riscv/tcg-target.opc.h diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index d5c419dff1..b2b3211bcb 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -9,6 +9,7 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) +REGS('v', ALL_VECTOR_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d334857226..ca9bafcb3c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -30,40 +30,18 @@ #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 +int riscv_vlen =3D -1; + #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "zero", - "ra", - "sp", - "gp", - "tp", - "t0", - "t1", - "t2", - "s0", - "s1", - "a0", - "a1", - "a2", - "a3", - "a4", - "a5", - "a6", - "a7", - "s2", - "s3", - "s4", - "s5", - "s6", - "s7", - "s8", - "s9", - "s10", - "s11", - "t3", - "t4", - "t5", - "t6" + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", }; #endif =20 @@ -100,6 +78,16 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_A5, TCG_REG_A6, TCG_REG_A7, + + /* Vector registers and TCG_REG_V0 reserved for mask. */ + TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, TCG_REG_V4, + TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, TCG_REG_V8, + TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, TCG_REG_V12, + TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, TCG_REG_V16, + TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, TCG_REG_V20, + TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, TCG_REG_V24, + TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, TCG_REG_V28, + TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, }; =20 static const int tcg_target_call_iarg_regs[] =3D { @@ -127,6 +115,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKin= d kind, int slot) #define TCG_CT_CONST_J12 0x1000 =20 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) +#define ALL_VECTOR_REGS MAKE_64BIT_MASK(33, 31) +#define ALL_DVECTOR_REG_GROUPS 0x5555555400000000 +#define ALL_QVECTOR_REG_GROUPS 0x1111111000000000 =20 #define sextreg sextract64 =20 @@ -475,6 +466,43 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, } } =20 +/* + * RISC-V vector instruction emitters + */ + +/* Vector registers uses the same 5 lower bits as GPR registers. */ +static void tcg_out_opc_reg_vec(TCGContext *s, RISCVInsn opc, + TCGReg d, TCGReg s1, TCGReg s2, bool vm) +{ + tcg_out32(s, encode_r(opc, d, s1, s2) | (vm << 25)); +} + +static void tcg_out_opc_reg_vec_i(TCGContext *s, RISCVInsn opc, + TCGReg rd, TCGArg imm, TCGReg vs2, bool = vm) +{ + tcg_out32(s, encode_r(opc, rd, (imm & 0x1f), vs2) | (vm << 25)); +} + +/* vm=3D0 (vm =3D false) means vector masking ENABLED. */ +#define tcg_out_opc_vv(s, opc, vd, vs2, vs1, vm) \ + tcg_out_opc_reg_vec(s, opc, vd, vs1, vs2, vm); + +/* + * In RISC-V, vs2 is the first operand, while rs1/imm is the + * second operand. + */ +#define tcg_out_opc_vx(s, opc, vd, vs2, rs1, vm) \ + tcg_out_opc_reg_vec(s, opc, vd, rs1, vs2, vm); + +#define tcg_out_opc_vi(s, opc, vd, vs2, imm, vm) \ + tcg_out_opc_reg_vec_i(s, opc, vd, imm, vs2, vm); + +/* + * Only unit-stride addressing implemented; may extend in future. + */ +#define tcg_out_opc_ldst_vec(s, opc, vs3_vd, rs1, vm) \ + tcg_out_opc_reg_vec(s, opc, vs3_vd, rs1, 0, vm); + /* * TCG intrinsics */ @@ -1881,6 +1909,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } =20 +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) +{ + switch (opc) { + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + switch (opc) { + default: + g_assert_not_reached(); + } +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + switch (opc) { + default: + return 0; + } +} + static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { @@ -2096,11 +2154,39 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } =20 +static void riscv_get_vlenb(void){ + /* Get vlenb for Vector: csrrs %0, vlenb, zero. */ + asm volatile("csrrs %0, 0xc22, x0" : "=3Dr"(riscv_vlen)); + riscv_vlen *=3D 8; +} + static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 + if (cpuinfo & CPUINFO_ZVE64X) { + /* We need to get vlenb for vector's extension */ + riscv_get_vlenb(); + tcg_debug_assert(riscv_vlen >=3D 64 && is_power_of_2(riscv_vlen)); + + if (riscv_vlen >=3D 256) { + tcg_target_available_regs[TCG_TYPE_V64] =3D ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] =3D ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V256] =3D ALL_VECTOR_REGS; + } else if (riscv_vlen =3D=3D 128) { + tcg_target_available_regs[TCG_TYPE_V64] =3D ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] =3D ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V256] =3D ALL_DVECTOR_REG_G= ROUPS; + } else if (riscv_vlen =3D=3D 64) { + tcg_target_available_regs[TCG_TYPE_V64] =3D ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] =3D ALL_DVECTOR_REG_G= ROUPS; + tcg_target_available_regs[TCG_TYPE_V256] =3D ALL_QVECTOR_REG_G= ROUPS; + } else { + g_assert_not_reached(); + } + } + tcg_target_call_clobber_regs =3D -1u; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); @@ -2123,6 +2209,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_V0); } =20 typedef struct { diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 1a347eaf6e..12a7a37aaa 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -28,42 +28,28 @@ #include "host/cpuinfo.h" =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_NB_REGS 32 +#define TCG_TARGET_NB_REGS 64 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 typedef enum { - TCG_REG_ZERO, - TCG_REG_RA, - TCG_REG_SP, - TCG_REG_GP, - TCG_REG_TP, - TCG_REG_T0, - TCG_REG_T1, - TCG_REG_T2, - TCG_REG_S0, - TCG_REG_S1, - TCG_REG_A0, - TCG_REG_A1, - TCG_REG_A2, - TCG_REG_A3, - TCG_REG_A4, - TCG_REG_A5, - TCG_REG_A6, - TCG_REG_A7, - TCG_REG_S2, - TCG_REG_S3, - TCG_REG_S4, - TCG_REG_S5, - TCG_REG_S6, - TCG_REG_S7, - TCG_REG_S8, - TCG_REG_S9, - TCG_REG_S10, - TCG_REG_S11, - TCG_REG_T3, - TCG_REG_T4, - TCG_REG_T5, - TCG_REG_T6, + TCG_REG_ZERO, TCG_REG_RA, TCG_REG_SP, TCG_REG_GP, + TCG_REG_TP, TCG_REG_T0, TCG_REG_T1, TCG_REG_T2, + TCG_REG_S0, TCG_REG_S1, TCG_REG_A0, TCG_REG_A1, + TCG_REG_A2, TCG_REG_A3, TCG_REG_A4, TCG_REG_A5, + TCG_REG_A6, TCG_REG_A7, TCG_REG_S2, TCG_REG_S3, + TCG_REG_S4, TCG_REG_S5, TCG_REG_S6, TCG_REG_S7, + TCG_REG_S8, TCG_REG_S9, TCG_REG_S10, TCG_REG_S11, + TCG_REG_T3, TCG_REG_T4, TCG_REG_T5, TCG_REG_T6, + + /* RISC-V V Extension registers */ + TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, =20 /* aliases */ TCG_AREG0 =3D TCG_REG_S0, @@ -156,6 +142,32 @@ typedef enum { =20 #define TCG_TARGET_HAS_tst 0 =20 +/* vector instructions */ +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v128 0 +#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_nand_vec 0 +#define TCG_TARGET_HAS_nor_vec 0 +#define TCG_TARGET_HAS_eqv_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + +#define TCG_TARGET_HAS_tst_vec 0 + #define TCG_TARGET_DEFAULT_MO (0) =20 #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/riscv/tcg-target.opc.h b/tcg/riscv/tcg-target.opc.h new file mode 100644 index 0000000000..b80b39e1e5 --- /dev/null +++ b/tcg/riscv/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) C-SKY Microsystems Co., Ltd. + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723549100; cv=none; d=zohomail.com; s=zohoarc; b=kFaxnaHSKiiZLgxJf0faT5I/toBVsP0eebqNkqZxbRl8AP/a0q+T8mWWgCLDvAONYMJTZxTM+z5tsLAcOpGwUNMfRlF0Hf3ZnefiQkO4FXnmdPFy+0XkO/yag0lAL63N4eqymzh4CkULtaJHcqJB2eJYpfO01g6gxvufuekiWbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723549100; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lvFNvEppiy993nwuTm8cniWhWLOsLV/kI8byv+ff5ms=; b=UkxSWqyxqwkMEXxzJIW7M6Vmg1ah35IXfisRTEZQiJQjRrW80RyaFJWQOdTI38BNJ/uUwlcz24O2zeIyftsVzdmBA2wA/bmf+CqsssqBefeOlenpLt6Vy4wtY4A53+LRfO4mOTDDrWxcvsMmt7ggq76rOBhuPjO/io20IIe1DHU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1723549100104533.0378580855179; Tue, 13 Aug 2024 04:38:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sdpqY-0004Aj-54; Tue, 13 Aug 2024 07:37:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sdpqW-00042D-Vv; Tue, 13 Aug 2024 07:37:49 -0400 Received: from out30-133.freemail.mail.aliyun.com ([115.124.30.133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sdpqU-0002eO-Ow; Tue, 13 Aug 2024 07:37:48 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WCp.8wQ_1723549060) by smtp.aliyun-inc.com; Tue, 13 Aug 2024 19:37:41 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549062; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=lvFNvEppiy993nwuTm8cniWhWLOsLV/kI8byv+ff5ms=; b=lVUFnwfACtW5IEf174T5odmFVaETqkssaO6XhSGmkkScDRtXDvTvJ8X3gCc69s30VIe15K76ZNkf3kSkX0zvdffRf6MdA3e9i3zF3kjDrUXZRsepAUsQJZh22RbtWFME/09MRqKftAf6rt6Lx0cDYXtZRFnQ7Df2KakqcD+ALho= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 05/15] tcg/riscv: Add riscv vset{i}vli support Date: Tue, 13 Aug 2024 19:34:26 +0800 Message-Id: <20240813113436.831-6-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.133; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1723549101515116600 Content-Type: text/plain; charset="utf-8" From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multiplier) Other vector operation parameters This configuration is crucial for defining subsequent vector operation behavior. To optimize performance, the configuration process is managed dynamically: 1. Reconfiguration using vset{i}vl{i} is necessary when SEW or vector register group width changes. 2. The vset instruction can be omitted when configuration remains unchanged. This optimization is only effective within a single TB. Each TB requires reconfiguration at its start, as the current state cannot be obtained from hardware. Signed-off-by: TANG Tiancheng Signed-off-by: Weiwei Li Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 121 +++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ca9bafcb3c..d17f523187 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -167,6 +167,18 @@ static bool tcg_target_const_match(int64_t val, int ct, * RISC-V Base ISA opcodes (IM) */ =20 +#define V_OPIVV (0x0 << 12) +#define V_OPFVV (0x1 << 12) +#define V_OPMVV (0x2 << 12) +#define V_OPIVI (0x3 << 12) +#define V_OPIVX (0x4 << 12) +#define V_OPFVF (0x5 << 12) +#define V_OPMVX (0x6 << 12) +#define V_OPCFG (0x7 << 12) + +#define V_SUMOP (0x0 << 20) +#define V_LUMOP (0x0 << 20) + typedef enum { OPC_ADD =3D 0x33, OPC_ADDI =3D 0x13, @@ -262,6 +274,11 @@ typedef enum { /* Zicond: integer conditional operations */ OPC_CZERO_EQZ =3D 0x0e005033, OPC_CZERO_NEZ =3D 0x0e007033, + + /* V: Vector extension 1.0 */ + OPC_VSETVLI =3D 0x57 | V_OPCFG, + OPC_VSETIVLI =3D 0xc0000057 | V_OPCFG, + OPC_VSETVL =3D 0x80000057 | V_OPCFG, } RISCVInsn; =20 /* @@ -354,6 +371,42 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uin= t32_t imm) return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); } =20 +typedef enum { + VTA_TU =3D 0, + VTA_TA, +} RISCVVta; + +typedef enum { + VMA_MU =3D 0, + VMA_MA, +} RISCVVma; + +typedef enum { + VSEW_E8 =3D 0, /* EW=3D8b */ + VSEW_E16, /* EW=3D16b */ + VSEW_E32, /* EW=3D32b */ + VSEW_E64, /* EW=3D64b */ +} RISCVVsew; + +typedef enum { + VLMUL_M1 =3D 0, /* LMUL=3D1 */ + VLMUL_M2, /* LMUL=3D2 */ + VLMUL_M4, /* LMUL=3D4 */ + VLMUL_M8, /* LMUL=3D8 */ + VLMUL_RESERVED, + VLMUL_MF8, /* LMUL=3D1/8 */ + VLMUL_MF4, /* LMUL=3D1/4 */ + VLMUL_MF2, /* LMUL=3D1/2 */ +} RISCVVlmul; +#define LMUL_MAX 8 + +static int32_t encode_vtype(RISCVVta vta, RISCVVma vma, + RISCVVsew vsew, RISCVVlmul vlmul) +{ + return (vma & 0x1) << 7 | (vta & 0x1) << 6 | (vsew & 0x7) << 3 | + (vlmul & 0x7); +} + /* * RISC-V instruction emitters */ @@ -483,6 +536,12 @@ static void tcg_out_opc_reg_vec_i(TCGContext *s, RISCV= Insn opc, tcg_out32(s, encode_r(opc, rd, (imm & 0x1f), vs2) | (vm << 25)); } =20 +static void tcg_out_opc_vec_config(TCGContext *s, RISCVInsn opc, + TCGReg rd, uint32_t avl, int32_t vtypei) +{ + tcg_out32(s, encode_i(opc, rd, avl, vtypei)); +} + /* vm=3D0 (vm =3D false) means vector masking ENABLED. */ #define tcg_out_opc_vv(s, opc, vd, vs2, vs1, vm) \ tcg_out_opc_reg_vec(s, opc, vd, vs1, vs2, vm); @@ -497,12 +556,68 @@ static void tcg_out_opc_reg_vec_i(TCGContext *s, RISC= VInsn opc, #define tcg_out_opc_vi(s, opc, vd, vs2, imm, vm) \ tcg_out_opc_reg_vec_i(s, opc, vd, imm, vs2, vm); =20 +#define tcg_out_opc_vconfig(s, opc, rd, avl, vtypei) \ + tcg_out_opc_vec_config(s, opc, rd, avl, vtypei); + /* * Only unit-stride addressing implemented; may extend in future. */ #define tcg_out_opc_ldst_vec(s, opc, vs3_vd, rs1, vm) \ tcg_out_opc_reg_vec(s, opc, vs3_vd, rs1, 0, vm); =20 +static void tcg_out_vsetvl(TCGContext *s, uint32_t avl, RISCVVta vta, + RISCVVma vma, RISCVVsew vsew, + RISCVVlmul vlmul) +{ + int32_t vtypei =3D encode_vtype(vta, vma, vsew, vlmul); + + if (avl < 32) { + tcg_out_opc_vconfig(s, OPC_VSETIVLI, TCG_REG_ZERO, avl, vtypei); + } else { + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, avl); + tcg_out_opc_vconfig(s, OPC_VSETVLI, TCG_REG_ZERO, TCG_REG_TMP0, vt= ypei); + } +} + +/* + * TODO: If the vtype value is not supported by the implementation, + * then the vill bit is set in vtype, the remaining bits in + * vtype are set to zero, and the vl register is also set to zero + */ + +static __thread unsigned prev_size; +static __thread unsigned prev_vece =3D MO_8; +static __thread bool vec_vtpye_init =3D true; + +#define get_vlmax(vsew) (riscv_vlen / (8 << vsew) * (LMUL_MAX)) +#define get_vec_type_bytes(type) (type >=3D TCG_TYPE_V64 ? \ + (8 << (type - TCG_TYPE_V64)) : 0) +#define encode_lmul(oprsz, vlenb) (ctzl(oprsz / vlenb)) + +static inline void tcg_target_set_vec_config(TCGContext *s, TCGType type, + unsigned vece) +{ + unsigned oprsz =3D get_vec_type_bytes(type); + + if (!vec_vtpye_init && (prev_size =3D=3D oprsz && prev_vece =3D=3D vec= e)) { + return ; + } + + RISCVVsew vsew =3D vece - MO_8 + VSEW_E8; + unsigned avl =3D oprsz / (1 << vece); + unsigned vlenb =3D riscv_vlen / 8; + RISCVVlmul lmul =3D oprsz > vlenb ? + encode_lmul(oprsz, vlenb) : VLMUL_M1; + tcg_debug_assert(avl <=3D get_vlmax(vsew)); + tcg_debug_assert(lmul <=3D VLMUL_RESERVED); + + prev_size =3D oprsz; + prev_vece =3D vece; + vec_vtpye_init =3D false; + tcg_out_vsetvl(s, avl, VTA_TA, VMA_MA, vsew, lmul); + return ; +} + /* * TCG intrinsics */ @@ -1914,6 +2029,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) { + TCGType type =3D vecl + TCG_TYPE_V64; + + if (vec_vtpye_init) { + tcg_target_set_vec_config(s, type, vece); + } switch (opc) { case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ @@ -2151,6 +2271,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 static void tcg_out_tb_start(TCGContext *s) { + vec_vtpye_init =3D true; /* nothing to do */ } =20 --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 Aug 2024 19:38:12 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549093; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=4caXpcnBVCZB2n4y1+rDuHT9XRwbTsjdRnqhWeySDsU=; b=oTlYcbzDCP287wd7SF+jMqh7QyJZDEyPYp1zcVixNcLp2erqi1MlXJF7AhdHUrnsEfetfC3XZRLlu0JGoiX4nm08QvglbSwdzhAEgagT1kGlRuGzoSHRb0kEUAVdm/k06wMNZOpft6ScpK8aDSgHH3sBHti5koowQ6Sc7tN4RrI= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 06/15] tcg/riscv: Implement vector load/store Date: Tue, 13 Aug 2024 19:34:27 +0800 Message-Id: <20240813113436.831-7-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 92 ++++++++++++++++++++++++++++++++-- 2 files changed, 91 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index aac5ceee2b..d73a62b0f2 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -21,3 +21,5 @@ C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) +C_O0_I2(v, r) +C_O1_I1(v, r) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d17f523187..f17d679d71 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -279,6 +279,15 @@ typedef enum { OPC_VSETVLI =3D 0x57 | V_OPCFG, OPC_VSETIVLI =3D 0xc0000057 | V_OPCFG, OPC_VSETVL =3D 0x80000057 | V_OPCFG, + + OPC_VLE8_V =3D 0x7 | V_LUMOP, + OPC_VLE16_V =3D 0x5007 | V_LUMOP, + OPC_VLE32_V =3D 0x6007 | V_LUMOP, + OPC_VLE64_V =3D 0x7007 | V_LUMOP, + OPC_VSE8_V =3D 0x27 | V_SUMOP, + OPC_VSE16_V =3D 0x5027 | V_SUMOP, + OPC_VSE32_V =3D 0x6027 | V_SUMOP, + OPC_VSE64_V =3D 0x7027 | V_SUMOP, } RISCVInsn; =20 /* @@ -810,6 +819,13 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc,= TCGReg data, case OPC_SD: tcg_out_opc_store(s, opc, addr, data, imm12); break; + case OPC_VSE8_V: + case OPC_VSE16_V: + case OPC_VSE32_V: + case OPC_VSE64_V: + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, imm12); + tcg_out_opc_ldst_vec(s, opc, data, TCG_REG_TMP0, true); + break; case OPC_LB: case OPC_LBU: case OPC_LH: @@ -819,6 +835,13 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc,= TCGReg data, case OPC_LD: tcg_out_opc_imm(s, opc, data, addr, imm12); break; + case OPC_VLE8_V: + case OPC_VLE16_V: + case OPC_VLE32_V: + case OPC_VLE64_V: + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, imm12); + tcg_out_opc_ldst_vec(s, opc, data, TCG_REG_TMP0, true); + break; default: g_assert_not_reached(); } @@ -827,14 +850,59 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc= , TCGReg data, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_LW : OPC_LD; + RISCVInsn insn; + + if (type < TCG_TYPE_V64) { + insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_LW : OPC_LD; + } else { + tcg_debug_assert(arg >=3D TCG_REG_V1); + switch (prev_vece) { + case MO_8: + insn =3D OPC_VLE8_V; + break; + case MO_16: + insn =3D OPC_VLE16_V; + break; + case MO_32: + insn =3D OPC_VLE32_V; + break; + case MO_64: + insn =3D OPC_VLE64_V; + break; + default: + g_assert_not_reached(); + } + } tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SW : OPC_SD; + RISCVInsn insn; + + if (type < TCG_TYPE_V64) { + insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SW : OPC_SD; + tcg_out_ldst(s, insn, arg, arg1, arg2); + } else { + tcg_debug_assert(arg >=3D TCG_REG_V1); + switch (prev_vece) { + case MO_8: + insn =3D OPC_VSE8_V; + break; + case MO_16: + insn =3D OPC_VSE16_V; + break; + case MO_32: + insn =3D OPC_VSE32_V; + break; + case MO_64: + insn =3D OPC_VSE64_V; + break; + default: + g_assert_not_reached(); + } + } tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 @@ -2030,11 +2098,25 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, const int const_args[TCG_MAX_OP_ARGS]) { TCGType type =3D vecl + TCG_TYPE_V64; + TCGArg a0, a1, a2; + + a0 =3D args[0]; + a1 =3D args[1]; + a2 =3D args[2]; =20 - if (vec_vtpye_init) { + if (!vec_vtpye_init && + (opc =3D=3D INDEX_op_ld_vec || opc =3D=3D INDEX_op_st_vec)) { + tcg_target_set_vec_config(s, type, prev_vece); + } else { tcg_target_set_vec_config(s, type, vece); } switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2198,6 +2280,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_qemu_st_a64_i64: return C_O0_I2(rZ, r); =20 + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_ld_vec: + return C_O1_I1(v, r); default: g_assert_not_reached(); } --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723549165; cv=none; d=zohomail.com; s=zohoarc; b=hgs9T26JQtvrM3FUx3I9joEDv6ruxSVV/f45zuX7HXLuuKOtkbdPFWprKWVeyczebhcqFuRoxTTQ9f9LjeDk+xlEU8zQ+J4UOtfKKEWeQA028ucEqsNcIiJpiNUXZpptRtD4Wdw4/6b2KpS2wjGgToBrIk2ADT7LcvRItIH6w2U= ARC-Message-Signature: i=1; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f17d679d71..f60913e805 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -288,6 +288,10 @@ typedef enum { OPC_VSE16_V =3D 0x5027 | V_SUMOP, OPC_VSE32_V =3D 0x6027 | V_SUMOP, OPC_VSE64_V =3D 0x7027 | V_SUMOP, + + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, + OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, + OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, } RISCVInsn; =20 /* @@ -641,6 +645,13 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) case TCG_TYPE_I64: tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); break; + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + tcg_debug_assert(ret > TCG_REG_V0 && arg > TCG_REG_V0); + tcg_target_set_vec_config(s, type, prev_vece); + tcg_out_opc_vv(s, OPC_VMV_V_V, ret, TCG_REG_V0, arg, true); + break; default: g_assert_not_reached(); } @@ -977,6 +988,33 @@ static void tcg_out_addsub2(TCGContext *s, } } =20 +static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned v= ece, + TCGReg dst, TCGReg src) +{ + tcg_target_set_vec_config(s, type, vece); + tcg_out_opc_vx(s, OPC_VMV_V_X, dst, TCG_REG_V0, src, true); + return true; +} + +static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned = vece, + TCGReg dst, TCGReg base, intptr_t offs= et) +{ + tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); + return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); +} + +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned = vece, + TCGReg dst, int64_t arg) +{ + if (arg < 16 && arg >=3D -16) { + tcg_target_set_vec_config(s, type, vece); + tcg_out_opc_vi(s, OPC_VMV_V_I, dst, TCG_REG_V0, arg, true); + return; + } + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); + tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); +} + static const struct { RISCVInsn op; bool swap; @@ -2111,6 +2149,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, tcg_target_set_vec_config(s, type, vece); } switch (opc) { + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_ld_vec: tcg_out_ld(s, type, a0, a1, a2); break; @@ -2282,6 +2323,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_st_vec: return C_O0_I2(v, r); + case INDEX_op_dup_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); default: --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723549179; cv=none; d=zohomail.com; s=zohoarc; b=WqqdKKhFrUIKxHVCeefYmeDuLPq6a7PuSoBAGTFLc9cobamCULttWclgscdzhsM58j0zRi39nwypNSO97buxkyBqOyt3FqMeyZP8bQkVa6b73XUfVRsmKPl7jYEIxlvb0bF4yJfO2DiVENh3E9bU3az9xAn2C7FxZyi+Ghyx/lg= ARC-Message-Signature: i=1; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d73a62b0f2..8a0de18257 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -23,3 +23,4 @@ C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) C_O1_I1(v, r) +C_O1_I2(v, v, v) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f60913e805..650b5eff1a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -289,6 +289,12 @@ typedef enum { OPC_VSE32_V =3D 0x6027 | V_SUMOP, OPC_VSE64_V =3D 0x7027 | V_SUMOP, =20 + OPC_VADD_VV =3D 0x57 | V_OPIVV, + OPC_VSUB_VV =3D 0x8000057 | V_OPIVV, + OPC_VAND_VV =3D 0x24000057 | V_OPIVV, + OPC_VOR_VV =3D 0x28000057 | V_OPIVV, + OPC_VXOR_VV =3D 0x2c000057 | V_OPIVV, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -2158,6 +2164,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_add_vec: + tcg_out_opc_vv(s, OPC_VADD_VV, a0, a1, a2, true); + break; + case INDEX_op_sub_vec: + tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2, true); + break; + case INDEX_op_and_vec: + tcg_out_opc_vv(s, OPC_VAND_VV, a0, a1, a2, true); + break; + case INDEX_op_or_vec: + tcg_out_opc_vv(s, OPC_VOR_VV, a0, a1, a2, true); + break; + case INDEX_op_xor_vec: + tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2177,6 +2198,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return 1; default: return 0; } @@ -2327,6 +2354,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); 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charset="utf-8" From: TANG Tiancheng 1.Address immediate value constraints in RISC-V Vector Extension 1.0 for comparison instructions. 2.Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target-con-str.h | 1 + tcg/riscv/tcg-target.c.inc | 188 +++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.opc.h | 3 + 4 files changed, 194 insertions(+) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 8a0de18257..23b391dd07 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -22,5 +22,7 @@ C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) +C_O0_I2(v, vK) C_O1_I1(v, r) C_O1_I2(v, v, v) +C_O1_I2(v, v, vK) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index b2b3211bcb..0aaad7b753 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -17,6 +17,7 @@ REGS('v', ALL_VECTOR_REGS) */ CONST('I', TCG_CT_CONST_S12) CONST('J', TCG_CT_CONST_J12) +CONST('K', TCG_CT_CONST_S5) CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 650b5eff1a..3f1e215e90 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,6 +113,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKin= d kind, int slot) #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 #define TCG_CT_CONST_J12 0x1000 +#define TCG_CT_CONST_S5 0x2000 =20 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(33, 31) @@ -160,6 +161,13 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_J12) && ~val >=3D -0x800 && ~val <=3D 0x7ff) { return 1; } + /* + * Sign extended from 5 bits: [-0x10, 0x0f]. + * Used for vector-immediate. + */ + if ((ct & TCG_CT_CONST_S5) && val >=3D -0x10 && val <=3D 0x0f) { + return 1; + } return 0; } =20 @@ -289,12 +297,39 @@ typedef enum { OPC_VSE32_V =3D 0x6027 | V_SUMOP, OPC_VSE64_V =3D 0x7027 | V_SUMOP, =20 + OPC_VMERGE_VIM =3D 0x5c000057 | V_OPIVI, + OPC_VMERGE_VVM =3D 0x5c000057 | V_OPIVV, + OPC_VMNAND_MM =3D 0x74000057 | V_OPMVV, + OPC_VADD_VV =3D 0x57 | V_OPIVV, OPC_VSUB_VV =3D 0x8000057 | V_OPIVV, OPC_VAND_VV =3D 0x24000057 | V_OPIVV, OPC_VOR_VV =3D 0x28000057 | V_OPIVV, OPC_VXOR_VV =3D 0x2c000057 | V_OPIVV, =20 + OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, + OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, + OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, + OPC_VMSNE_VV =3D 0x64000057 | V_OPIVV, + OPC_VMSNE_VI =3D 0x64000057 | V_OPIVI, + OPC_VMSNE_VX =3D 0x64000057 | V_OPIVX, + + OPC_VMSLTU_VV =3D 0x68000057 | V_OPIVV, + OPC_VMSLTU_VX =3D 0x68000057 | V_OPIVX, + OPC_VMSLT_VV =3D 0x6c000057 | V_OPIVV, + OPC_VMSLT_VX =3D 0x6c000057 | V_OPIVX, + OPC_VMSLEU_VV =3D 0x70000057 | V_OPIVV, + OPC_VMSLEU_VX =3D 0x70000057 | V_OPIVX, + OPC_VMSLE_VV =3D 0x74000057 | V_OPIVV, + OPC_VMSLE_VX =3D 0x74000057 | V_OPIVX, + + OPC_VMSLEU_VI =3D 0x70000057 | V_OPIVI, + OPC_VMSLE_VI =3D 0x74000057 | V_OPIVI, + OPC_VMSGTU_VI =3D 0x78000057 | V_OPIVI, + OPC_VMSGTU_VX =3D 0x78000057 | V_OPIVX, + OPC_VMSGT_VI =3D 0x7c000057 | V_OPIVI, + OPC_VMSGT_VX =3D 0x7c000057 | V_OPIVX, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -575,6 +610,15 @@ static void tcg_out_opc_vec_config(TCGContext *s, RISC= VInsn opc, #define tcg_out_opc_vi(s, opc, vd, vs2, imm, vm) \ tcg_out_opc_reg_vec_i(s, opc, vd, imm, vs2, vm); =20 +#define tcg_out_opc_vim_mask(s, opc, vd, vs2, imm) \ + tcg_out_opc_reg_vec_i(s, opc, vd, imm, vs2, false); + +#define tcg_out_opc_vvm_mask(s, opc, vd, vs2, vs1) \ + tcg_out_opc_reg_vec(s, opc, vd, vs1, vs2, false); + +#define tcg_out_opc_mvv(s, opc, vd, vs2, vs1, vm) \ + tcg_out_opc_reg_vec(s, opc, vd, vs1, vs2, vm); + #define tcg_out_opc_vconfig(s, opc, rd, avl, vtypei) \ tcg_out_opc_vec_config(s, opc, rd, avl, vtypei); =20 @@ -1037,6 +1081,22 @@ static const struct { [TCG_COND_GTU] =3D { OPC_BLTU, true } }; =20 +static const struct { + RISCVInsn opc; + bool swap; +} tcg_cmpcond_to_rvv_vv[] =3D { + [TCG_COND_EQ] =3D { OPC_VMSEQ_VV, false }, + [TCG_COND_NE] =3D { OPC_VMSNE_VV, false }, + [TCG_COND_LT] =3D { OPC_VMSLT_VV, false }, + [TCG_COND_GE] =3D { OPC_VMSLE_VV, true }, + [TCG_COND_GT] =3D { OPC_VMSLT_VV, true }, + [TCG_COND_LE] =3D { OPC_VMSLE_VV, false }, + [TCG_COND_LTU] =3D { OPC_VMSLTU_VV, false }, + [TCG_COND_GEU] =3D { OPC_VMSLEU_VV, true }, + [TCG_COND_GTU] =3D { OPC_VMSLTU_VV, true }, + [TCG_COND_LEU] =3D { OPC_VMSLEU_VV, false } +}; + static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, TCGReg arg2, TCGLabel *l) { @@ -1054,6 +1114,79 @@ static void tcg_out_brcond(TCGContext *s, TCGCond co= nd, TCGReg arg1, tcg_out_opc_branch(s, op, arg1, arg2, 0); } =20 +static const struct { + RISCVInsn op; + bool expand; +} tcg_cmpcond_to_rvv_vx[] =3D { + [TCG_COND_EQ] =3D { OPC_VMSEQ_VX, false }, + [TCG_COND_NE] =3D { OPC_VMSNE_VX, false }, + [TCG_COND_GT] =3D { OPC_VMSGT_VX, false }, + [TCG_COND_LE] =3D { OPC_VMSLE_VX, false }, + [TCG_COND_LT] =3D { OPC_VMSLT_VX, false }, + [TCG_COND_LTU] =3D { OPC_VMSLTU_VX, false }, + [TCG_COND_GTU] =3D { OPC_VMSGTU_VX, false }, + [TCG_COND_LEU] =3D { OPC_VMSLEU_VX, false }, + [TCG_COND_GE] =3D { OPC_VMSLT_VX, true }, + [TCG_COND_GEU] =3D { OPC_VMSLTU_VX, true }, +}; + +static void tcg_out_cmp_vec_vx(TCGContext *s, TCGCond cond, TCGReg arg1, + tcg_target_long arg2) +{ + RISCVInsn op; + + tcg_debug_assert((unsigned)cond < ARRAY_SIZE(tcg_cmpcond_to_rvv_vx)); + op =3D tcg_cmpcond_to_rvv_vx[cond].op; + tcg_debug_assert(op !=3D 0); + + tcg_out_opc_vx(s, op, TCG_REG_V0, arg1, arg2, true); + if (tcg_cmpcond_to_rvv_vx[cond].expand) { + tcg_out_opc_mvv(s, OPC_VMNAND_MM, TCG_REG_V0, TCG_REG_V0, + TCG_REG_V0, false); + } +} + +static const struct { + RISCVInsn op; + int min; + int max; + bool adjust; +} tcg_cmpcond_to_rvv_vi[] =3D { + [TCG_COND_EQ] =3D { OPC_VMSEQ_VI, -16, 15, false }, + [TCG_COND_NE] =3D { OPC_VMSNE_VI, -16, 15, false }, + [TCG_COND_GT] =3D { OPC_VMSGT_VI, -16, 15, false }, + [TCG_COND_LE] =3D { OPC_VMSLE_VI, -16, 15, false }, + [TCG_COND_LT] =3D { OPC_VMSLE_VI, -15, 16, true }, + [TCG_COND_GE] =3D { OPC_VMSGT_VI, -15, 16, true }, + [TCG_COND_LEU] =3D { OPC_VMSLEU_VI, 0, 15, false }, + [TCG_COND_GTU] =3D { OPC_VMSGTU_VI, 0, 15, false }, + [TCG_COND_LTU] =3D { OPC_VMSLEU_VI, 1, 16, true }, + [TCG_COND_GEU] =3D { OPC_VMSGTU_VI, 1, 16, true }, +}; + +static void tcg_out_cmp_vec_vi(TCGContext *s, TCGCond cond, TCGReg arg1, + tcg_target_long arg2) +{ + RISCVInsn op; + signed imm_min, imm_max; + + tcg_debug_assert((unsigned)cond < ARRAY_SIZE(tcg_cmpcond_to_rvv_vi)); + op =3D tcg_cmpcond_to_rvv_vi[cond].op; + tcg_debug_assert(op !=3D 0); + imm_min =3D tcg_cmpcond_to_rvv_vi[cond].min; + imm_max =3D tcg_cmpcond_to_rvv_vi[cond].max; + + if (arg2 >=3D imm_min && arg2 <=3D imm_max) { + if (tcg_cmpcond_to_rvv_vi[cond].adjust) { + arg2 -=3D 1; + } + tcg_out_opc_vi(s, op, TCG_REG_V0, arg1, arg2, true); + } else { + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, arg2); + tcg_out_cmp_vec_vx(s, cond, arg1, TCG_REG_TMP0); + } +} + #define SETCOND_INV TCG_TARGET_NB_REGS #define SETCOND_NEZ (SETCOND_INV << 1) #define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) @@ -2179,6 +2312,33 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_xor_vec: tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); break; + case INDEX_op_rvv_cmpcond_vec: + { + RISCVInsn op; + if (const_args[1]) { + tcg_out_cmp_vec_vi(s, a2, a0, a1); + } else { + op =3D tcg_cmpcond_to_rvv_vv[a2].opc; + tcg_debug_assert(op !=3D 0); + + if (tcg_cmpcond_to_rvv_vv[a2].swap) { + TCGReg t =3D a0; + a0 =3D a1; + a1 =3D t; + } + tcg_out_opc_vv(s, op, TCG_REG_V0, a0, a1, true); + } + } + break; + case INDEX_op_rvv_merge_vec: + if (const_args[2]) { + /* vd[i] =3D v0.mask[i] ? imm : vs2[i] */ + tcg_out_opc_vim_mask(s, OPC_VMERGE_VIM, a0, a1, a2); + } else { + /* vd[i] =3D v0.mask[i] ? vs1[i] : vs2[i] */ + tcg_out_opc_vvm_mask(s, OPC_VMERGE_VVM, a0, a1, a2); + } + break; case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2189,10 +2349,31 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { + va_list va; + TCGv_vec v0, v1; + TCGArg a2, a3; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); + switch (opc) { + case INDEX_op_cmp_vec: + { + a3 =3D va_arg(va, TCGArg); + vec_gen_3(INDEX_op_rvv_cmpcond_vec, type, vece, + tcgv_vec_arg(v1), a2, a3); + tcg_gen_mov_vec(v0, tcg_constant_vec_matching(v0, vece, 0)); + vec_gen_3(INDEX_op_rvv_merge_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(v0), + tcgv_i64_arg(tcg_constant_i64(-1))); + } + break; default: g_assert_not_reached(); } + va_end(va); } =20 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) @@ -2204,6 +2385,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_or_vec: case INDEX_op_xor_vec: return 1; + case INDEX_op_cmp_vec: + return -1; default: return 0; } @@ -2360,6 +2543,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_or_vec: case INDEX_op_xor_vec: return C_O1_I2(v, v, v); + case INDEX_op_cmp_vec: + case INDEX_op_rvv_merge_vec: + return C_O1_I2(v, v, vK); + case INDEX_op_rvv_cmpcond_vec: + return C_O0_I2(v, vK); default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.opc.h b/tcg/riscv/tcg-target.opc.h index b80b39e1e5..2f23453c35 100644 --- a/tcg/riscv/tcg-target.opc.h +++ b/tcg/riscv/tcg-target.opc.h @@ -10,3 +10,6 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ + +DEF(rvv_cmpcond_vec, 0, 2, 1, IMPLVEC) +DEF(rvv_merge_vec, 1, 2, 0, IMPLVEC) --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1723549240; cv=none; d=zohomail.com; s=zohoarc; b=GfkftdKrCEcNCCT9C29RemQFiyCUfiAaXpAmhZ1RyXj4oT/6nDMnfhqM0YFsEyj3+z+2OxdoybNr+Qq/4mWEjMuU+qewrPViTNKmjegXT9c8KkOZiofW+d3xLU7KR6DPvG1gG3XeJfJBklsUyaPy23p5JdsLLfqRBENjvEvSyIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723549240; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 13 +++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 23b391dd07..781b18a09e 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -24,5 +24,6 @@ C_O2_I4(r, r, rZ, rZ, rM, rM) C_O0_I2(v, r) C_O0_I2(v, vK) C_O1_I1(v, r) +C_O1_I1(v, v) C_O1_I2(v, v, v) C_O1_I2(v, v, vK) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 3f1e215e90..a33c634dbb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -306,7 +306,9 @@ typedef enum { OPC_VAND_VV =3D 0x24000057 | V_OPIVV, OPC_VOR_VV =3D 0x28000057 | V_OPIVV, OPC_VXOR_VV =3D 0x2c000057 | V_OPIVV, + OPC_VXOR_VI =3D 0x2c000057 | V_OPIVI, =20 + OPC_VRSUB_VX =3D 0xc000057 | V_OPIVX, OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, @@ -2312,6 +2314,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_xor_vec: tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); break; + case INDEX_op_not_vec: + tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true); + break; + case INDEX_op_neg_vec: + tcg_out_opc_vx(s, OPC_VRSUB_VX, a0, a1, TCG_REG_ZERO, true); + break; case INDEX_op_rvv_cmpcond_vec: { RISCVInsn op; @@ -2384,6 +2392,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: + case INDEX_op_not_vec: + case INDEX_op_neg_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2537,6 +2547,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_dupm_vec: case INDEX_op_ld_vec: return C_O1_I1(v, r); + case INDEX_op_neg_vec: + case INDEX_op_not_vec: + return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 12a7a37aaa..401696d639 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -151,8 +151,8 @@ typedef enum { #define TCG_TARGET_HAS_nand_vec 0 #define TCG_TARGET_HAS_nor_vec 0 #define TCG_TARGET_HAS_eqv_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 Aug 2024 19:40:49 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549250; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=9VkrOMAWW8/SEoudX6ekSYnxMFrp7IwQFP/8vxd4SUM=; b=jOEcpjbd1tonEnxkW44VE6YevlgNLegR1twkmZAVINdnko8XILYNnl2uA0vphzw2/A49jqBnhL96t7im/44Awb5iVuLSvUseO+WSHmATAdFLVDxAp3OITZMVvyq48muxa2EVaerdVyTz4RctcNYuBnzyiLPI3H03EN6htVm/icc= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops Date: Tue, 13 Aug 2024 19:34:32 +0800 Message-Id: <20240813113436.831-12-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index a33c634dbb..af21b4593c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -309,6 +309,13 @@ typedef enum { OPC_VXOR_VI =3D 0x2c000057 | V_OPIVI, =20 OPC_VRSUB_VX =3D 0xc000057 | V_OPIVX, + + OPC_VMUL_VV =3D 0x94000057 | V_OPMVV, + OPC_VSADD_VV =3D 0x84000057 | V_OPIVV, + OPC_VSSUB_VV =3D 0x8c000057 | V_OPIVV, + OPC_VSADDU_VV =3D 0x80000057 | V_OPIVV, + OPC_VSSUBU_VV =3D 0x88000057 | V_OPIVV, + OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, @@ -2320,6 +2327,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_neg_vec: tcg_out_opc_vx(s, OPC_VRSUB_VX, a0, a1, TCG_REG_ZERO, true); break; + case INDEX_op_mul_vec: + tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2, true); + break; + case INDEX_op_ssadd_vec: + tcg_out_opc_vv(s, OPC_VSADD_VV, a0, a1, a2, true); + break; + case INDEX_op_sssub_vec: + tcg_out_opc_vv(s, OPC_VSSUB_VV, a0, a1, a2, true); + break; + case INDEX_op_usadd_vec: + tcg_out_opc_vv(s, OPC_VSADDU_VV, a0, a1, a2, true); + break; + case INDEX_op_ussub_vec: + tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmpcond_vec: { RISCVInsn op; @@ -2394,6 +2416,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_xor_vec: case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2555,6 +2582,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_and_vec: case INDEX_op_or_vec: case INDEX_op_xor_vec: + case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return C_O1_I2(v, v, v); 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 25 +++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index af21b4593c..c9c69d61fb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -316,6 +316,11 @@ typedef enum { OPC_VSADDU_VV =3D 0x80000057 | V_OPIVV, OPC_VSSUBU_VV =3D 0x88000057 | V_OPIVV, =20 + OPC_VMAX_VV =3D 0x1c000057 | V_OPIVV, + OPC_VMAXU_VV =3D 0x18000057 | V_OPIVV, + OPC_VMIN_VV =3D 0x14000057 | V_OPIVV, + OPC_VMINU_VV =3D 0x10000057 | V_OPIVV, + OPC_VMSEQ_VV =3D 0x60000057 | V_OPIVV, OPC_VMSEQ_VI =3D 0x60000057 | V_OPIVI, OPC_VMSEQ_VX =3D 0x60000057 | V_OPIVX, @@ -2342,6 +2347,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_ussub_vec: tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true); break; + case INDEX_op_smax_vec: + tcg_out_opc_vv(s, OPC_VMAX_VV, a0, a1, a2, true); + break; + case INDEX_op_smin_vec: + tcg_out_opc_vv(s, OPC_VMIN_VV, a0, a1, a2, true); + break; + case INDEX_op_umax_vec: + tcg_out_opc_vv(s, OPC_VMAXU_VV, a0, a1, a2, true); + break; + case INDEX_op_umin_vec: + tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmpcond_vec: { RISCVInsn op; @@ -2421,6 +2438,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2587,6 +2608,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_cmp_vec: case INDEX_op_rvv_merge_vec: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 21251f8b23..35e7086ad7 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -162,7 +162,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 Aug 2024 19:41:52 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549312; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Y+04WUHZKv3BiSHUJr1oSJGcQ6Dcci8AL1zDFCEkDbE=; b=nhlSutHLVJmyI+puS8U5BcCcnRMM0xyqbSjAGAT7DjupsI+wM18N3TCR44VQfxohQWyXuqVcmmD6NhSvDkg/XYx6d9XV1cz/N3qj21RHG/8AucQHUO1pAP8TwJZFar211J/ntG897wj0Fix/kWS8xoDmTlZMtgaW38jhdEGI3v8= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops Date: Tue, 13 Aug 2024 19:34:34 +0800 Message-Id: <20240813113436.831-14-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 38 ++++++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 781b18a09e..6510bb5605 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -27,3 +27,4 @@ C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I2(v, v, v) C_O1_I2(v, v, vK) +C_O1_I2(v, v, r) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c9c69d61fb..467437e175 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -344,6 +344,13 @@ typedef enum { OPC_VMSGT_VI =3D 0x7c000057 | V_OPIVI, OPC_VMSGT_VX =3D 0x7c000057 | V_OPIVX, =20 + OPC_VSLL_VV =3D 0x94000057 | V_OPIVV, + OPC_VSLL_VX =3D 0x94000057 | V_OPIVX, + OPC_VSRL_VV =3D 0xa0000057 | V_OPIVV, + OPC_VSRL_VX =3D 0xa0000057 | V_OPIVX, + OPC_VSRA_VV =3D 0xa4000057 | V_OPIVV, + OPC_VSRA_VX =3D 0xa4000057 | V_OPIVX, + OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, OPC_VMV_V_I =3D 0x5e000057 | V_OPIVI, OPC_VMV_V_X =3D 0x5e000057 | V_OPIVX, @@ -2359,6 +2366,24 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_umin_vec: tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true); break; + case INDEX_op_shls_vec: + tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2, true); + break; + case INDEX_op_shrs_vec: + tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2, true); + break; + case INDEX_op_sars_vec: + tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2, true); + break; + case INDEX_op_shlv_vec: + tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2, true); + break; + case INDEX_op_shrv_vec: + tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2, true); + break; + case INDEX_op_sarv_vec: + tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2, true); + break; case INDEX_op_rvv_cmpcond_vec: { RISCVInsn op; @@ -2442,6 +2467,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return 1; case INDEX_op_cmp_vec: return -1; @@ -2612,7 +2643,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); case INDEX_op_cmp_vec: case INDEX_op_rvv_merge_vec: return C_O1_I2(v, v, vK); diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 35e7086ad7..41c6c446e8 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -158,8 +158,8 @@ typedef enum { #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549344; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=znLSvwkEqr0aaxGpxr2NfOv6XEcqHqV18gv2KQ2YOyM=; b=SDmLkI4J6JA2hhd3O+Aq9zUg7K4GD6Qeu1b4CTQ6UIhq8ZDEl8vUCbq4ZDdCROw54hFM91Z64H7sfzGwzXWuTlQt949efm2LTe68FwgtELmqdv18HG1rAs5waWOLZB1+FB+sEmoLZyJ0Sfk0Z3Z8VO6gzW88U1NESGUJ711uZLM= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops Date: Tue, 13 Aug 2024 19:34:35 +0800 Message-Id: <20240813113436.831-15-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 107 ++++++++++++++++++++++++++++++++++++- tcg/riscv/tcg-target.h | 8 +-- tcg/riscv/tcg-target.opc.h | 3 ++ 3 files changed, 113 insertions(+), 5 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 467437e175..59d23ed622 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -345,10 +345,13 @@ typedef enum { OPC_VMSGT_VX =3D 0x7c000057 | V_OPIVX, =20 OPC_VSLL_VV =3D 0x94000057 | V_OPIVV, + OPC_VSLL_VI =3D 0x94000057 | V_OPIVI, OPC_VSLL_VX =3D 0x94000057 | V_OPIVX, OPC_VSRL_VV =3D 0xa0000057 | V_OPIVV, + OPC_VSRL_VI =3D 0xa0000057 | V_OPIVI, OPC_VSRL_VX =3D 0xa0000057 | V_OPIVX, OPC_VSRA_VV =3D 0xa4000057 | V_OPIVV, + OPC_VSRA_VI =3D 0xa4000057 | V_OPIVI, OPC_VSRA_VX =3D 0xa4000057 | V_OPIVX, =20 OPC_VMV_V_V =3D 0x5e000057 | V_OPIVV, @@ -2384,6 +2387,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sarv_vec: tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2, true); break; + case INDEX_op_rvv_shli_vec: + tcg_out_opc_vi(s, OPC_VSLL_VI, a0, a1, a2, true); + break; + case INDEX_op_rvv_shri_vec: + tcg_out_opc_vi(s, OPC_VSRL_VI, a0, a1, a2, true); + break; + case INDEX_op_rvv_sari_vec: + tcg_out_opc_vi(s, OPC_VSRA_VI, a0, a1, a2, true); + break; case INDEX_op_rvv_cmpcond_vec: { RISCVInsn op; @@ -2422,7 +2434,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, u= nsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1; + TCGv_vec v0, v1, v2, c1, t1; + TCGv_i32 t2; TCGArg a2, a3; =20 va_start(va, a0); @@ -2442,6 +2455,81 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, tcgv_i64_arg(tcg_constant_i64(-1))); } break; + case INDEX_op_shli_vec: + if (a2 > 31) { + t2 =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(t2, (int32_t)a2); + tcg_gen_shls_vec(vece, v0, v1, t2); + tcg_temp_free_i32(t2); + } else { + vec_gen_3(INDEX_op_rvv_shli_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), a2); + } + break; + case INDEX_op_shri_vec: + if (a2 > 31) { + t2 =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(t2, (int32_t)a2); + tcg_gen_shrs_vec(vece, v0, v1, t2); + tcg_temp_free_i32(t2); + } else { + vec_gen_3(INDEX_op_rvv_shri_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), a2); + } + break; + case INDEX_op_sari_vec: + if (a2 > 31) { + t2 =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(t2, (int32_t)a2); + tcg_gen_sars_vec(vece, v0, v1, t2); + tcg_temp_free_i32(t2); + } else { + vec_gen_3(INDEX_op_rvv_sari_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), a2); + } + break; + case INDEX_op_rotli_vec: + t1 =3D tcg_temp_new_vec(type); + tcg_gen_shli_vec(vece, t1, v1, a2); + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - a2); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + case INDEX_op_rotls_vec: + t1 =3D tcg_temp_new_vec(type); + t2 =3D tcg_temp_new_i32(); + tcg_gen_sub_i32(t2, tcg_constant_i32(8 << vece), + temp_tcgv_i32(arg_temp(a2))); + tcg_gen_shrs_vec(vece, v0, v1, t2); + tcg_gen_shls_vec(vece, t1, v1, temp_tcgv_i32(arg_temp(a2))); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + tcg_temp_free_i32(t2); + break; + case INDEX_op_rotlv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + c1 =3D tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, c1, v2); + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + case INDEX_op_rotrv_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + t1 =3D tcg_temp_new_vec(type); + c1 =3D tcg_constant_vec(type, vece, 8 << vece); + tcg_gen_sub_vec(vece, t1, c1, v2); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; default: g_assert_not_reached(); } @@ -2475,6 +2563,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sarv_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_shri_vec: + case INDEX_op_shli_vec: + case INDEX_op_sari_vec: + case INDEX_op_rotls_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_rotli_vec: return -1; default: return 0; @@ -2628,6 +2723,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) return C_O1_I1(v, r); case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_rotli_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + case INDEX_op_rvv_shli_vec: + case INDEX_op_rvv_shri_vec: + case INDEX_op_rvv_sari_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2646,10 +2748,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: return C_O1_I2(v, v, v); case INDEX_op_shls_vec: case INDEX_op_shrs_vec: case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: return C_O1_I2(v, v, r); case INDEX_op_cmp_vec: case INDEX_op_rvv_merge_vec: diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 41c6c446e8..eb5129a976 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -154,10 +154,10 @@ typedef enum { #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 0 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_roti_vec -1 +#define TCG_TARGET_HAS_rots_vec -1 +#define TCG_TARGET_HAS_rotv_vec -1 +#define TCG_TARGET_HAS_shi_vec -1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 diff --git a/tcg/riscv/tcg-target.opc.h b/tcg/riscv/tcg-target.opc.h index 2f23453c35..3a010e853e 100644 --- a/tcg/riscv/tcg-target.opc.h +++ b/tcg/riscv/tcg-target.opc.h @@ -13,3 +13,6 @@ =20 DEF(rvv_cmpcond_vec, 0, 2, 1, IMPLVEC) DEF(rvv_merge_vec, 1, 2, 0, IMPLVEC) +DEF(rvv_shli_vec, 1, 1, 1, IMPLVEC) +DEF(rvv_shri_vec, 1, 1, 1, IMPLVEC) +DEF(rvv_sari_vec, 1, 1, 1, IMPLVEC) --=20 2.43.0 From nobody Sun Nov 24 11:08:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 13 Aug 2024 19:42:55 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723549376; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=QF8w0EuuEt8vPs/L1xgYqK4lMhxVSFP0lyikbUU8wuM=; b=FzHoDT+oXt9fXw0AEwVQLfpcGzJk+sTPlDeopCa+cE3kBZtf4zB07XF7hiXXbbw9JvBDDzw/MT8rmPmLSoGqfa8WotsmtNqrXvfAG/lxaaYMCD1Ayp9pHUPkq3KAfMQqDJskt/y3PSyI4Je1G6+WMdcFcBdWX8SaOshP/AfPKHk= From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, TANG Tiancheng Subject: [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native Date: Tue, 13 Aug 2024 19:34:36 +0800 Message-Id: <20240813113436.831-16-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index eb5129a976..fe6c50e49e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -143,9 +143,13 @@ typedef enum { #define TCG_TARGET_HAS_tst 0 =20 /* vector instructions */ -#define TCG_TARGET_HAS_v64 0 -#define TCG_TARGET_HAS_v128 0 -#define TCG_TARGET_HAS_v256 0 +extern int riscv_vlen; +#define have_rvv ((cpuinfo & CPUINFO_ZVE64X) && \ + (riscv_vlen >=3D 64)) + +#define TCG_TARGET_HAS_v64 have_rvv +#define TCG_TARGET_HAS_v128 have_rvv +#define TCG_TARGET_HAS_v256 have_rvv #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_nand_vec 0 --=20 2.43.0